Innovative Ideas for Predictable Success
      Issue 4, 2009

  NEWS  |   CALENDAR  |   PAST ISSUES SYNOPSYS.COM  |  CONTACT US

Industry Insight Industry Insight
The New Economics of Verification
A more intelligent approach to verification can help design teams control the rising cost of chip design, according to Manoj Gandhi, Synopsys.  FULL STORY

Technology Insight Technology Update
Parasitic Extraction for Next-Generation Custom ICs
Designing custom and mixed-signal circuits for the latest process technology demands high-accuracy extraction that is tuned for simulation productivity, explains Shekhar Kapoor, Synopsys.  FULL STORY

Using MATLAB and High-Level Synthesis for DSP Implementation
Design teams are looking to hardware to implement better performance and lower power DSP algorithms. Chris Eddington, Synopsys, describes Synphony HLS – a new high-level synthesis tool for ASIC and FPGA.  FULL STORY


Industry Insight  RECENT ARTICLES - ISSUE 3 - 2009
 New Technology Reduces Total Cost of Design
 Collaborating for System-on-Chip Design Success at 32/28nm
 Coping with Modern AMS Verification Challenges
 In-Design Physical Verification

Industry Insight  SYNOPSYS NEWSLETTERS
 DesignWare Technical Bulletin
 TCAD Newsletter
Vertical
Register Buttom

SoC BENCHMARK
Design re-spins
The number of design re-spins has fallen over the past two years.