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Synopsys Chosen by Realtek as Its Primary EDA Partner
Synopsys TetraMAX ATPG Cuts Test Development Schedule at Arrow Electronics
Media Advisory/Alert: Synopsys EDA Interoperability Forum to Feature Subodh Bapat Keynote on Green Computing
Synopsys Extends DFTMAX Compression to Reduce the Cost of Pin-Limited Test
Technology scaling a “virtuous cycle”....
Navraj Nandra
First USB 3.0 Products available in....
Eric Huang
Is Successful System Design About....
Frank Schirrmeister
Phases vs. Threads
jlgray
Verification Peace, Love and....
Tom Borgstrom
Isolation Cell Usage Tips
Godwin Maben
NOV
10
Automotive Electronics Reliability: A Software to Silicon Methodology
Webinar
NOV
11
StarRC Custom Extraction for Custom IC Design
Webinar
NOV
11
The Recipe for Successful Formal Verification: Proper Constraining of Your Design
Webinar
DEC
01
Simulation of Advanced Semiconductor Devices Including High-k/Metal-gate Transistors and FinFETs
Webinar
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New! DFTMAX Compression
Higher compression for pin-limited test methodologies
In-Design Rail Analysis
Identify and fix voltage drop and electromigration issues during physical implementation
New! IC Validator
IC Validator speeds time to tapeout with In-Design Physical Verification
CustomSim Circuit Simulation
Unified AMS verification technologies deliver 4x performance improvement
HAPS-A31
Stratix III Rapid Prototyping and Algorithm Acceleration Board
Chalk Talk - Introducing Synphony HLS
Webinar: IC Compiler Ecosystem
Webinar: Accelerate Time-to-Quality with Power-Aware Test
Combining Formal Verification with Simulation: The Best of Both Worlds
Webinar: Reduce Energy Consumption for Datapath Designs
32nm Collaboration Video – Innovation Optimized!
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