To handle increasing communication system speeds, the XAUI standard is designed to take a 10 Gbps serial stream and divided into four 2.5Gbps serial streams that run over copper traces and chip to chip connections using 8B10B coding at 3.125Gbaud. By taking advantage of copper links, higher performance communications applications can be cost effectively deployed.

The XAUI PHY integrates high-speed mixed-signal custom CMOS circuitry and is compliant with the XAUI base specification. While extremely low in power consumption and area requirements, Synopsys' XAUI PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity.

DesignWare XAUI PHY Datasheet
DesignWare XAUI PHY for Common Platform Processes Datasheet
 

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• Supports a wide range of configurations including 1.0v & 1.2v core supplies and 2.5v & 3.3v I/O supplies
• Supports IEEE 802.3ae
• Supports popular 90 nm and 130 nm processes
• Excellent performance margin and receiver sensitivity
• On board scope and diagnostics for fast system verification
• Supports popular 90nm and 130nm processes
• Extremely low power consumption per lane resulting in significant savings

XAUI PHY, CP 65G, x4	STARs	Subscribe
XAUI PHY, CP 65G, x8	STARs	Subscribe
XAUI PHY, TSMC 130G, x4	STARs	Subscribe
XAUI PHY, TSMC 130LV, x4	STARs	Subscribe
XAUI PHY, TSMC 130LV, x8	STARs	Subscribe
XAUI PHY, TSMC 65GP, x4	STARs	Subscribe
XAUI PHY, TSMC 65GP, x8	STARs	Subscribe
XAUI PHY, TSMC 65LP, x4	STARs	Subscribe
XAUI PHY, TSMC 90G, x4	STARs	Subscribe
XAUI PHY, TSMC 90G, x8	STARs	Subscribe

Description	XAUI PHY, CP 65G, x4
Name	dwc_xauiphy-cp65g-x4
Version	3.7a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Common Platform Datasheet DesignWare XAUI PHY for Common Platform Processes Datasheet Databook DesignWare Cores XAUI PHY For Common Platform 65-nm G (Wirebond/Flip-Chip) … Datasheet DesignWare XAUI PHY Datasheet Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity White Paper The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
Download	dwc_xauiphy-cp65g-x4
Description	XAUI PHY, CP 65G, x8
Name	dwc_xauiphy-cp65g-x8
Version	3.6a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Common Platform Datasheet DesignWare XAUI PHY for Common Platform Processes Datasheet Databook DesignWare Cores XAUI PHY For Common Platform 65-nm G (Wirebond/Flip-Chip) … Datasheet DesignWare XAUI PHY Datasheet Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity White Paper The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
Download	dwc_xauiphy-cp65g-x8
Description	XAUI PHY, TSMC 130G, x4
Name	dwc_xauiphy-tsmc130g-x4
Version	2.5b
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Common Platform Datasheet DesignWare XAUI PHY for Common Platform Processes Datasheet Databook DesignWare Cores XAUI PHY For TSMC 130-nm G (Wirebond/Flip-Chip) Databook Datasheet DesignWare XAUI PHY Datasheet Evaluation Databook DesignWare Cores XAUI PHY For TSMC 130-nm G (Wirebond/Flip-Chip) Evaluation Databook Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity White Paper The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
Download	dwc_xauiphy-tsmc130g-x4
Description	XAUI PHY, TSMC 130LV, x4
Name	dwc_xauiphy-tsmc130lv-x4
Version	2.5b
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Common Platform Datasheet DesignWare XAUI PHY for Common Platform Processes Datasheet Databook DesignWare Cores XAUI PHY For TSMC 130-nm LV (Wirebond/Flip-Chip) Databook Datasheet DesignWare XAUI PHY Datasheet Evaluation Databook DesignWare Cores XAUI PHY For TSMC 130-nm LV (Wirebond/Flip-Chip) Evaluation … Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity White Paper The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
Download	dwc_xauiphy-tsmc130lv-x4
Description	XAUI PHY, TSMC 130LV, x8
Name	dwc_xauiphy-tsmc130lv-x8
Version	2.5b
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Common Platform Datasheet DesignWare XAUI PHY for Common Platform Processes Datasheet Databook DesignWare Cores XAUI PHY For TSMC 130-nm LV (Wirebond/Flip-Chip) Databook Datasheet DesignWare XAUI PHY Datasheet Evaluation Databook DesignWare Cores XAUI PHY For TSMC 130-nm LV (Wirebond/Flip-Chip) Evaluation … Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity White Paper The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
Download	dwc_xauiphy-tsmc130lv-x8
Description	XAUI PHY, TSMC 65GP, x4
Name	dwc_xauiphy-tsmc65gp-x4
Version	3.5a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Databook DesignWare Cores XAUI PHY For TSMC 65-nm GP (Wirebond/Flip-Chip) Databook Evaluation Databook DesignWare Cores XAUI PHY For TSMC 65-nm GP (Wirebond/Flip-Chip) Evaluation … Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity
Download	dwc_xauiphy-tsmc65gp-x4
Description	XAUI PHY, TSMC 65GP, x8
Name	dwc_xauiphy-tsmc65gp-x8
Version	3.2b
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Databook DesignWare Cores XAUI PHY For TSMC 65-nm GP (Wirebond/Flip-Chip) Databook Evaluation Databook DesignWare Cores XAUI PHY For TSMC 65-nm GP (Wirebond/Flip-Chip) Evaluation … Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity
Download	dwc_xauiphy-tsmc65gp-x8
Description	XAUI PHY, TSMC 65LP, x4
Name	dwc_xauiphy-tsmc65lp-x4
Version	3.2a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Databook DesignWare Cores XAUI PHY For TSMC 65-nm LP (Wirebond/Flip-Chip) Databook Evaluation Databook DesignWare Cores XAUI PHY For TSMC 65-nm LP (Wirebond/Flip-Chip) Evaluation Databook White Paper The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
Download	dwc_xauiphy-tsmc65lp-x4
Description	XAUI PHY, TSMC 90G, x4
Name	dwc_xauiphy-tsmc90g-x4
Version	2.6a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Common Platform Datasheet DesignWare XAUI PHY for Common Platform Processes Datasheet Databook DesignWare Cores XAUI PHY For TSMC 90-nm G (Wirebond/Flip-Chip) Databook Datasheet DesignWare XAUI PHY Datasheet Evaluation Databook DesignWare Cores XAUI PHY For TSMC 90-nm G (Wirebond/Flip-Chip) Evaluation Databook Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity White Paper The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
Download	dwc_xauiphy-tsmc90g-x4
Description	XAUI PHY, TSMC 90G, x8
Name	dwc_xauiphy-tsmc90g-x8
Version	2.6a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	Implementation IP
Documentation	Show Documents... Hide Documents... Common Platform Datasheet DesignWare XAUI PHY for Common Platform Processes Datasheet Databook DesignWare Cores XAUI PHY For TSMC 90-nm G (Wirebond/Flip-Chip) Databook Datasheet DesignWare XAUI PHY Datasheet Evaluation Databook DesignWare Cores XAUI PHY For TSMC 90-nm G (Wirebond/Flip-Chip) Evaluation Databook Success Stories DesignWare PHY IP Saves Two Man Years of Engineering Effort for 10GBASE-T Copper … High Quality DesignWare IP for PCI Express, XAUI and DDR Lowers Power and Area for iVivity White Paper The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
Download	dwc_xauiphy-tsmc90g-x8