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The Synopsys DesignWare® Hi-Speed USB 2.0 On-The-Go (HS OTG) PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip, USB 2.0 integration in OTG applications. The USB 2.0 OTG PHY includes all the required logical, geometric, and physical design files to implement USB 2.0 Hi-Speed OTG capability in a system-on-chip (SoC) design and to manufacture it in the designated foundry. The USB 2.0 OTG PHY is available in 90-nanometer (nm), 0.13-micron, and 0.18-micron CMOS digital logic processes. Alternatively, design services are available for porting the USB 2.0 OTG PHY to other semiconductor processes. DesignWare USB 2.0 PHY Datasheet
- Complete mixed-signal physical layer (PHY) for single-chip USB 2.0 OTG applications
- USB 2.0 Transceiver Macrocell Interface (UTMI+ Level 3) Specification
- USB 2.0 Device automatic switching between full- and high-speed modes
- Host Device automatic switching between full-, high- and low-speed modes
- 8-bit interface at 60-MHz operation and 16-bit interface at 30-MHz operation chip
- Designed for rapid integration with Synopsys' USB 2.0 On-The-Go controller
- Designed for minimal power dissipation for low-power and bus-powered devices
- Low-power design enables host enumeration of an unpowered device
- Sea-wall and decoupling structures reduce on-chip noise
- Suspend, Resume and Remote Wakeup mode support
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