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The DesignWare PHY IP for PCI Express 3.0, operating at 8.0 GT/s, meets the demand for increased bandwidth and narrower interconnect links in the graphics, data center, storage and networking infrastructure applications. Compatible with the PCIe 3.0 and PIPE specifications, it allows designers to optimize performance and power while maintaining interoperability with existing devices. The IP is designed to exceed the electrical specification of the PCI Express specification in areas such as jitter, margin and receive sensitivity, delivering a robust design without sacrificing performance. Also included are advanced built-in diagnostic capabilities and ATE test vectors which require no special process options, providing ease of integration and high production yields.
As the leading provider of PCI Express IP, Synopsys offers a complete PCI Express 3.0 IP solution, including digital controllers, PHY and verification IP from a single vendor. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 8.0 Gbps PCI Express interface into their high performance SoC designs. DesignWare IP for PCI Express 3.0 PHY Datasheet
DesignWare IP for PCI Express Complete Solution Datasheet
- Compliant with the PCI Express 3.0 (8.0 GT/s), 2.0 (5.0 GT/s) and 1.1 (2.5 GT/s) specifications
- Designed for integration in root complex, endpoint, dual-mode and switch applications
- Supports a wide range of PCI Express bus widths (up to x16 support)
- Exceeds electrical specifications in areas of margin and receive sensitivity for a robust design
- Unique, built-in diagnostics enables visibility into link performance
- Automatic Test Equipment (ATE) test vectors for complete, at-speed production testing
- Industry's leading, complete PCI Express 3.0 IP solution: digital controllers, PHY and verification IP
- Supports advanced 40-nm processes with roadmap to smaller geometries
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