The DesignWare PHY IP for PCI Express 2.0, operating at 5.0 Gbps, meets the demand for increased bandwidth and narrower interconnect links in the data center, storage and networking infrastructure applications. Compatible with the PCIe 2.0 and PIPE specifications, it allows designers to optimize performance and power while maintaining interoperability with existing devices. The IP exceeds electrical specification in areas such as jitter, margin and receive sensitivity, delivering a robust design without sacrificing performance. Also included are advanced built-in diagnostic capabilities and ATE test vectors which require no special process options, provides ease of integration and high production yields.As the leading provider of PCI Express IP, Synopsys offers the IP industry's only complete, silicon-proven PCI Express 2.0 IP solution, including digital controllers, PHY and verification IP from a single vendor. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 5.0 Gbps PCI Express interface into their high performance SoC designs.DesignWare IP for PCI Express 2.0 PHY Datasheet DesignWare IP for PCI Express Complete Solution Datasheet
DesignWare IP for PCI Express 2.0 Complete Solution Demo
See a live demonstration of the 45-nm DesignWare PHY and controller IP for PCI Express® 2.0 operating in a single-lane configuration at 5 GT/s.
The demonstration verifies 5 GT/s operation using the PCI® Tree software and executes Reads and Writes between the demo hardware and a PC to show throughput performance levels.
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