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HOME  IP INTERFACE AND STANDARDS IP PCI EXPRESS DESIGNWARE ROOT PORT CORE FOR PCI EXPRESS
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| DesignWare Root Port Core for PCI Express |
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The DesignWare® Root Port (RC) Core for PCI Express® implements a configurable and scalable Root Complex interface for integration into ASICs and FPGAs providing designers with a high-quality IP that reduces risk and improves time-to-market. The silicon-proven DesignWare RC core is compliant to the latest PCI-SIG® and PIPE specifications and has been extensively validated with multiple HW platforms, PHYs and PCIe verification suites. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.
The synthesizable core integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies. The core is available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimization of size, power, and throughput. DesignWare PCI Express cores are fully compliant with the PCI Express Base Specification 3.0, 2.0 and 1.1 and are used to power the industry's PCI Express compliance testing at PCI-SIG Compliance Workshops. DesignWare IP for PCI Express Complete Solution Datasheet
DesignWare IP for PCI Express Root Port Core Datasheet
DesignWare IP for PCI Express to AMBA 2.0 AHB Bridge Datasheet
DesignWare IP for PCI Express to AMBA 3 AXI Bridge Datasheet
- Designed according to the PCI Express 3.0, 2.0 and 1.1 specifications, including the latest errata
- Supports PIPE PHY interface definition including variable clock and variable data
- Supports 8.0, 5.0 and 2.5 Gbps line rates
- Architecture supports x1, x2, x4, x8, and x16 lanes
- Available in 32, 64 and 128 bit data path widths for maximum flexibility
- Optimal on-chip memory utilization and low latency
- Bypass, cut-through and store-and-forward receive queues
- Full power management support
- Advanced Error Reporting
- Optional ECC on the RAMs
- Optional Parity on the datapath and RAM
- ASIC and FPGA support
- Optional support for AMBA 3 AXI and AHB interfaces
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