The DesignWare® Endpoint (EP) Cores for PCI Express® implements a configurable and scalable Endpoint interface for integration into ASICs and FPGAs providing designers with a high-quality IP that reduces risk and improves time-to-market. The silicon-proven DesignWare EP core is compliant to the latest PCI-SIG® and PIPE specifications and has been extensively validated with multiple HW platforms, PHYs and PCIe verification suites. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.The synthesizable core integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies. The core is available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimization of size, power, and throughput. DesignWare PCI Express cores are fully compliant with the PCI Express Base Specification 3.0, 2.0 and 1.1 and are used to power the industry's PCI Express compliance testing at PCI-SIG Compliance Workshops.DesignWare IP for PCI Express Complete Solution Datasheet DesignWare IP for PCI Express Endpoint Core Datasheet DesignWare IP for PCI Express Endpoint LE Core Datasheet DesignWare IP for PCI Express Single Root I/O Virtualization Datasheet DesignWare IP for PCI Express to AMBA 2.0 AHB Bridge Datasheet DesignWare IP for PCI Express to AMBA 3 AXI Bridge Datasheet
DesignWare IP for PCI Express 2.0 Complete Solution Demo
See a live demonstration of the 45-nm DesignWare PHY and controller IP for PCI Express® 2.0 operating in a single-lane configuration at 5 GT/s.
The demonstration verifies 5 GT/s operation using the PCI® Tree software and executes Reads and Writes between the demo hardware and a PC to show throughput performance levels.
RSS