Synopsys XGMAC DesignWare® Core (DWC) is compliant with the IEEE 802.3ae specification. It interfaces to the PHY layer through the XGMII interface, and to the system through a FIFO interface. It is a highly configurable and eases SoC integration which allows it to tailor its feature set to the target application supporting speeds of 1G, 2.5G or 10G. The XGMAC can be integrated with the DWC Ethernet PCS and the DWC XAUI PHY cores from Synopsys to provide a complete 10 Gigabit Ethernet solution.DesignWare XAUI PHY Datasheet DesignWare XAUI PHY for Common Platform Processes Datasheet DesignWare XGMAC 10G Ethernet MAC Datasheet