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Synopsys DesignWare DDR3/2 SDRAM Memory Controller

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The Synopsys DesignWare® DDR3/2 SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR3/2 physical layer (PHY) in a DDR3 or DDR2 memory subsystem servicing data rates up to 2133Mbps. The MCTL is a full-featured memory controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training.

 

DesignWare DDR3/2 IP Demo at 1600 Mbps
Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.

Graham Allan
Product Marketing Manager, Memory Interface IP
Vishal Thareja
Test Engineer

  • Provides a complete, single vendor DDR3/2 SDRAM interface IP solution, when combined with the DesignWare DDR3/2 PHY IP
  • Supports JEDEC-standard DDR3 and DDR2 protocols (JESD79-3 and JESD79-2, respectively)
  • Supports data rates up to 2133Mbps
  • Uses a 4:1 data width conversion (also known as X4) from host interface to DDRn
    • MCTL clock is half the clock frequency of the memory channel for ease of digital logic timing closure
  • Includes a configurable multi-port arbiter with up to 32 host ports using Host Memory Interface (HMI) or AMBA 3 AXI
    • Programmable ultra-high priority port (port 0), typically a CPU port
  • Separate configuration port using Controller Register Interface (CRI) or AMBA 3 AXI with independent clocking
  • Command re-ordering and scheduling to maximize memory bus utilization
    • Command reordering between banks based on bank status
    • Programmable priority arbitration and anti-starvation mechanisms
    • Configurable per-command priority with up to eight priority levels; also serves as a per-port priority
  • Integrated DDR3/2 PHY Utility Block (PUB) - Automated RTL algorithms for PHY initialization/calibration and production test (for use with PUB-compatible DWC DDR3/2 PHYs)
  • Automatic scheduling of activate and precharge commands
  • Automatic scheduling of refreshes
  • Supports memory interfaces of 8 to 64 bits in 8 bit increments (up to 72 bits with ECC)
  • Programmable ECC generation, checking, and correction
  • Support for up to four external memory ranks
  • Programmable timing parameters support DDR3/gDDR2/DDR2 SDRAM components from various vendors
    • Extended register fields to permit interfacing to non-standard devices
DDR3/DDR2 Memory Controller (MCTL)STARsSubscribe

  Description DDR3/DDR2 Memory Controller (MCTL)
  Name dwc_ddr3_mctl
  Version 1.20a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type Implementation IP
  Documentation
  Download dw_iip_DWC_ddr3_mctl
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