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The DesignWare Verification IP (VIP) for I2C provides an efficient and simple way to verify the I2C
bi-directional two-wire bus. The Synopsys DesignWare VIP for I2C is fully compliant with version 2.1
of the Philip's I2C Bus Specification. It supports standard, fast, and high speed operations. The model has a rich set of configuration parameters to set clock synchronization and generation of the Serial Clock Line (SCL) to meet all clocking requirements. It also operates as a Master, Slave, or both. The role of the model can change dynamically according to the stimulus applied to the model-no configuration parameters are needed to switch between them. As a Master, the model can Start/Stop all possible transfers. In addition, as a Slave device it can detect Start/Stop conditions and perform data transfers according to the initiator request. DesignWare I2C Verification IP Datasheet
- Full I2C Master and Slave functionality
- Start, repeat start and stop for all possible transfers
- Supports all I2C clocking speeds
- 7b/10b configurable slave address
- Allows testing of varied bus traffic for Read,Write, General Call
- Supports scoreboard feature for end to end data integrity check
- Bus-accurate timing
- Notifies the testbench of significant events such as transactions, warnings, and protocol errors
- Includes protocol-based scenario generation
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