minPower Components
Low power datapath architectures and instantiable IP extends battery life in mobile applications and reduces power consumption for SoCs
Boosting Yield and Increasing Quality with Power-Aware Test and Small Delay Defect Testing
Overview
During this FREE technical webinar, we will provide an overview of new capabilities in DFTMAX™ compression and TetraMAX® ATPG that manage device power consumption at the tester, resulting in higher yield. Also, we will review technology developed at Synopsys that can help you create tests to detect defects creating small delays, thereby increasing your manufacturing test quality.
Who should attend: DFT Engineers, Design Engineers and Engineering Managers
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