| Efficient & Accurate Memory Timing & Power Analysis using CustomSim |
With the growing complexity of device models and the increasing impact on timing and power measurements from physical layout effects, accurate memory verification within a reasonable timeframe is a necessity. This webinar highlihgts memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time. Learn how Synopsys’ CustomSim™ solution is being used today for accurate and efficient memory timing and power analysis.
Bradley Geden, Product Marketing Manager
Dec 15, 2009 |
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| Everything You Always Wanted to Know About Low Power Verification |
In this webinar, you will learn why verification has fundamentally changed for low power designs and how Synopsys’ VCS with MVSIM and MVRC comprehensively and accurately meet the verification challenges. You will also hear about how these tools embody the principles outlined in the recently published Verification Methodology Manual for Low Power (VMM-LP).
Synopsys
Jul 14, 2009 |
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| Increase Design Confidence with CustomSim |
In this webinar you will learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement. Increase design confidence by finding electrical rule violations and power management failures rapidly with a comprehensive set of static and dynamic native circuit checks.
Synopsys
Apr 28, 2009 |
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| Verifying Complex Power-managed Designs |
An overview of approaches that address the difficult task of verifying low power designs.
Synopsys
Dec 18, 2008 |
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| Leakage Mitigation in ARM Processor-based Systems |
Leakage mitigation techniques such as power gating, state retention and dynamic threshold scaling have been shown to significantly reduce standby power consumption.
Alan Gibbons, Principal Engineer at Synopsys, Inc.
John Biggs, Consultant Engineer at ARM Ltd.
Dec 18, 2007 |
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| A Structured Methodology for Verifying Low Power Designs |
Power management and low power design introduce a new assortment of bugs and failure mechanisms to IC designs. The task of verification, already a critical path to the delivery of the chip, now needs to take on additional tests and flows to ensure the power management scheme is functional.
Synopsys
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