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Verification Martial Arts
In SystemVerilog, unlike C, you don’t have to explictly free dynamically allocated class instances. Like most modern programming languages, SystemVerilog includes a garbage collector that frees memory that is no longer needed.
Janick Bergeron
Magic Blue Smoke
Based on my interactions with many designers for the past few years, most common techniques in practice/proven today are
Godwin Maben
The Standards Game
Hello, everyone interested in EDA interoperability and fans of The Standards Game. I’d like to invite you to join me at the 21st Synopsys EDA Interoperability Forum, sponsored by Sun Microsystems.
Karen Bartleson
Analog Insights
The Verilog-AMS Technical Subcommittee of Accellera held another in a series of conference call discussions on Tuesday Oct-7, to further explore the topic of AMS Assertions.
Mike Demler
All Synopsys Blogs
NEW! CUSTOMSIM WEBINAR
Efficient & Accurate Memory Timing & Power Analysis using CustomSim
DAC 2009 VIDEOLOG
VCS: Solutions for Tough Verification Challenges
VMM-LP Tutorial Video
A Structured Methodology for Verifying Low Power Designs
VMM FOR LOW POWER
Get your copy of the Verification Methodology Manual for Low Power (VMM-LP)
DAC 2009 VIDEOLOG
Coping with Modern AMS Verification Challenges
News
Toshiba Information Systems (Japan) Standardizes on VMM-LP Low Power....
Synopsys MVSIM Adopted for Low Power Verification of STw8500 Mobile SoC Platform
Synopsys Delivers 2x Verification Speed-up with VCS Multicore Technology
Synopsys Unveils CustomSim Unified Circuit Simulation Solution
Synopsys Introduces Discovery 2009 Delivering Faster, Unified Verification Solutions
ARM, Renesas Technology and Synopsys Define Industry's First Low-Power....
Synopsys Introduces the Eclypse Low Power Solution
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All Synopsys News
Articles
Low-Power Design Portal Serializes VMM-LP Chapters
Verifying Low Power Designs
Why Voltage-aware Verification Strategy Counts
Moore’s Law vs. Low Power
Low Power Verification Methodology: Is this a Case of Natural Evolution?
Power and Verification Always Matter
Chip-verification and -design flow focuses on low power
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Blogs
Verification Martial Arts
Magic Blue Smoke
The Standards Game
Analog Insights
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White Papers
Low Power Verification for Multi-rail Cells
Decoupling Capacitance Estimation, Implementation and Verification: A Practical Approach for Deep Submicron SoCs
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Webinars
Efficient & Accurate Memory Timing & Power Analysis using CustomSim
Everything You Always Wanted to Know About Low Power Verification
Increase Design Confidence with CustomSim
Verifying Complex Power-managed Designs
Leakage Mitigation in ARM Processor-based Systems
A Structured Methodology for Verifying Low Power Designs
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Videos
VMM-LP Tutorial Video
DAC 2009: Coping with Modern AMS Challenges
DAC 2009: Solutions for Tough Verification Challenges
The Unique Challenge of Low Power Verification
The Birth of the VMM-LP
How Does the VMM-LP Benefit the Industry?
VMM User Forum Lunch Event: ARM, Ltd.
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Discovery Platform
Eclypse Low Power Solution
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