“Prototyping with FPGAs is a good solution for the problems that arise in designing our ASICs, and the Certify software approach is a good way to go, mainly due to the automated partitioning. For large, complex designs, it is less work, effort, and money versus hand partitioning. This is why we use the Certify product exclusively in this specific part of our design flow.”
Tom Hilgerdenaar, Project Team Leader for Systems Engineering, Handheld Group, ATI Technologies

“The integration between the emulator and the prototyping board was achieved in one week instead of four weeks as was originally scheduled.”
Rolf Singer, Mobile Communications Development Manager, Philips

“The Certify tool includes in a single environment features like Verilog-VHDL mixed language, partitioning, clock-gating handling, and a fast synthesis engine. Even if you can find some of these features in other tools, they are not available in a single environment.”
Francesco Sforza, Dynamic Verification Manager Central R&D, STMicroelectronics

“Only HAPS gives us the performance and control that we need whilst also being reliable, portable, and of course, flexible enough to protect our investment.”
Javier Jimenez, ASIC Design Manager, DS2