Overview
The Certify software is the leading implementation and partitioning tool for ASIC designers who use FPGA-based prototypes to verify their designs. Certify provides a quick and easy method for partitioning large ASIC designs onto multi-FPGA prototyping boards and includes powerful features that make it easy to adapt to existing device flows; speeding the verification process and helping to ease time to market challenges.

Key Features

• Includes easy to use graphical user interface (GUI) flow guide
• Allows automatic and/or manual partitioning
• Supports Synopsys Design Constraints for timing management
• Tightly integrated with Confirma hardware 
• Supports multi-core parallel processing for faster runtimes
• Supports most leading FPGA devices
• Includes industry standard Synplify Premier synthesis engine
  



Figure 1 Flow based graphical interface guides the user

Design Implementation
In order to prototype an ASIC design using FPGAs, certain design elements must be converted to structures that are recognizable by FPGA implementation tools. These elements, such as ASIC gate-level components or gated-clock tree structures, can be very difficult and time-consuming to edit manually.  The Certify software automatically recognizes and converts these ASIC-specific constructs into equivalent FPGA structures.

Partitioning
Certify’s automated mode partitions basic designs quickly with minimal user intervention by employing an intuitive, flow-driven graphical user interface (GUI).  For more complex designs, this flow-driven GUI will guide the user through the partitioning process and provide utilities such as I/O pin multiplexing designed to reduce the number of I/O pins between FPGA partitions.    Users can realize functional partition solutions quickly and use Certify’s advanced features to optimize these solutions.

Performance
The Certify tool supports system timing constraints, defined in industry standard Synopsys Design Constraint (SDC) format - ensuring that the overall ASIC timing is matched in the multi-FPGA implementation.  The Certify software can also provide a timing report outlining the possible performance of the prototype prior to programming the hardware. With Certify, users are assured that the timing constraints for the ASIC are achieved by the equivalent multi-FPGA prototyping implementation.

Confirma Flow Integration
Certify is tightly integrated into the Confirma Rapid Prototyping Platform - the complete ASIC verification hardware and software solution. Board descriptions for HAPS High-performance ASIC Prototyping Systems are built into the Certify tool allowing immediate productivity with almost no set-up time.  Certify software assures optimum performance because it automatically takes advantage of HAPS signals to provide high speed time domain multiplexing which ensures the fastest available connections between FPGAs. Certify uses the world-leading FPGA synthesis engine, Synplify Premier, to achieve the best possible mapping to the target FPGA. The Synplify Premier tool’s integration with the Identify Pro Visibility Debugging and Enhancement tool offers advanced debug capabilities to monitor signals in critical areas of a design.  

Figure 2 Certify is the key to Multi-FPGA Implementation, a part of the Confirma Rapid Prototyping Plus Solution