This white paper provides a detailed overview of VCS multicore technology, which improves verification performance by taking advantage of advances in the compute infrastructure. VCS multicore technology cuts verification time in half by harnessing the power of modern multicore CPUs and allows designers to identify performance bottlenecks and distribute time-consuming activities across multiple cores for faster functional verification and debug. Automatic partitioning and load balancing, event synchronization and memory optimization make VCS multicore unique for high-performance functional verification. Multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler optimization technique to deliver unmatched verification performance for large-scale designs for chip-level and system-level verification.
Usha Gaira and Sanjay Sawant

Multi-voltage designs have become increasingly common in order to achieve low power. Multiple supply rails are an essential part of multi-voltage designs. Assuming that all output pins in a logic cone are related to a single supply voltage can cause functional failures in silicon or excessive power loss. Consequently, verification tools need to understand the relationship between the driving voltage rails and the impact on each output pin to accurately resolve the logic values. Synopsys’ Eclypse solution provides an infrastructure to capture the necessary information and MVSIM and MVRC are able to use the information to accurately verify multi-rail designs and lead to silicon success. This white paper discusses the challenges faced with static and dynamic verification of multi-rail cells in the context of low power designs.
Prapanna Tiwari, Synopsys, Inc.

How do you know when you have run enough random tests? A constraint-driven random environment requires comprehensive coverage data, which often leads to information overload.
Nancy Pratt, Dwight Eddy

Register structure and memory modeling is a very complex task of any verification methodology.
Paul Lungu, Bo Zhu

Verification is one of the biggest challenges for System-on-Chip (SoC) designs, and traditional methods have run out of steam.
Charles Li, Ashesh Doshi

Today’s chip design requires extensive system-level simulations to ensure that the right architectural trade-offs are made.
Janick Bergeron, Scientist, Synopsys, Inc.

This document identifies the major differences between the e language as defined by the IEEE P1647/ D6 draft standard and the SystemVerilog language as defined by the IEEE Std. 1800™ 2005 standard.
Janick Bergeron Synopsys Scientist