Increasingly, verification engineers are deploying formal verification tools with simulation to solve today’s toughest verification problems. Properly constraining your design can mean the difference between success and failure when deploying formal tools. In this webinar, you will learn all about constraints and how their proper specification and use will help you quickly achieve your verification goals.
Krishna Balachandran, Director of Marketing, Synopsys; Dan Benua, Principal Engineer, Synopsys; Mandar Munishwar, Corporate Applications Engineer, Synopsys; and Xiaolin Chen, Corporate Applications Engineer, Synopsys
Nov 11, 2009

In this webinar, you will learn how VCS multicore technology allows users to reduce verification time for long-running tests by leveraging their multicore computing infrastructure. We will cover VCS multicore technology’s two flexible use models – application-level parallelism (ALP), which allows users to simultaneously simulate assertions, coverage and plotting concurrently on multiple cores, and design-level parallelism (DLP), which enables the concurrent simulation of multiple instances of a core, several partitions of a large design or an optimized combination of both. Following the detailed technical presentation, an interactive Q&A session with our panel of experts takes place.
Chiang, Product Marketing Manager, Synopsys; Usha Gaira, Corporate Applications Engineer, Synopsys; Amitabh Chand, Corporate Applications Engineering Manager, Synopsys; and Jatinder Goraya, Research and Development Engineer, Synopsys
Oct 27, 2009

VMM is the most widely adopted and proven verification methodology in the industry, with production-deployment on over 500 projects, tens of millions of lines of user code and more than 50 published user papers. VMM base classes, VMM Applications (such as RAL and Performance Analyzer) and VMM for Low Power (VMM-LP) are deployed worldwide to address the toughest verification challenges. In this webinar, you will learn about the latest developments in VMM. Our VMM experts will cover recent enhancements, including TLM 2.0 support, improved block-to-top reuse heirarchical phasing and several additional ease-of-use deployment features. Following the technical presentation an interactive Q&A session will take place.
Albert Chiang, Product Marketing Manager; Yassine Eben Amine, Applications Consultant; Kiran Maiya, Senior Corporate Applications Engineer; and Adiel Khan, Methodology Corporate Applications Engineer
Oct 13, 2009

Achieving complete verification of today's complex designs is, at best, a difficult and time consuming task that requires a combination of verification technologies. Design/verification teams use formal techniques to exhaustively prove functionality of small blocks, while resorting to simulation for full-chip verification. One of the barriers to using formal techniques has been the difficulty in leveraging an existing simulation environment. It has also been difficult to correlate the coverage information from formal tools with that from simulation. In this webinar, you will learn how Synopsys' Magellan seamlessly integrates formal verification with simulation to remove these barriers.
Krishna Balachandran, Director of Verifiation Marketing; Xiaolin Chen, Corporate Applications Engineer; Mandar Munishwar Corporate Applications Engineer; Dan Benua, Principal Engineer
Sep 10, 2009

The Discovery Visualization Environment (DVE) is a next-generation, full-featured debug and visualization environment within the VCS functional verification solution. DVE offers unified debug and analysis of Verilog, VHDL, C/C++/SystemC, SystemVerilog Assertion/Design/Testbench and analog waveform. In this webinar, you will hear how DVE can ease debug of RTL and learn about a number of DVE's advanced features, including coverage, planning, and interactive debug of a VMM verification environment with SystemC.
Albert Chiang, Technical Marketing Manager; Yasser Khan, Applications Engineer; Don Walters, R&D Manager
May 11, 2009

In this webinar you will learn how the constraint solver technology in VCS can increase design quality while accelerating verification and minimizing cost. It introduces the concept of constrained-random verification, including the SystemVerilog constraint syntax and its use in a verification methodology such as VMM. In addition, the speakers address debugging and profiling of constraints and discuss a few "tips and tricks" that help simplify constraint writing. Following the technical presentation, there is a formal Q&A session with a panel of Synopsys verification experts.
Synopsys
Apr 06, 2009

The continuing trend for larger, more complex designs has made it more critical than ever for verification engineers to increase their productivity.
Max Steven McMaster
Jul 15, 2008