Overview
VCS®, with multicore technology, delivers a 2x verification speed-up that helps users find design bugs early in the product development cycle. VCS multicore technology cuts down verification time by running the design, testbench, assertions, coverage and debug in parallel on machines with multiple cores. The combination of performance; advanced bug-finding technologies; Echo testbench coverage convergence for faster closure; a built-in debug and visualization environment; support for all popular design and verification languages including Verilog, VHDL, SystemVerilog, OpenVera, and SystemC™ and the proven VMM methodology help VCS users develop high-quality designs. The VCS solution’s advanced bug-finding technologies include full-featured Native Testbench (NTB), complete assertions and comprehensive code and functional coverage to find more design bugs faster and easier. Additionally, the VCS Verification Library provides high-quality VIP for today’s most popular bus standards. The VCS solution’s powerful debug and visualization environment minimizes the turnaround time to find and fix design bugs. VCS with MVSIM and MVRC delivers innovative voltageaware verification techniques to find bugs related to modern low power designs.

VCS Datasheet

Multicore support
VCS multicore technology allows users to cut down verification time for long-running tests. VCS offers two robust use models: design-level parallelism (DLP) and application-level parallelism (ALP). DLP enables users to concurrently simulate multiple instances of a core, several partitions of a large design, or a combination of the two. Application-level parallelism (ALP) allows users to run testbenches, assertions, coverage and debugging concurrently on multiple cores. The combination of DLP and ALP optimizes VCS performance over multicore CPUs. VCS multicore technology also supports design-level auto-partioning, file system database (FSDB) parallel dumping, and switching activity interchange format (SAIF) parallel dumping.

Full-featured, native testbench and industry-leading SystemVerilog support
VCS Native Testbench (NTB) provides built-in natively-compiled support for fullfeatured SystemVerilog and OpenVera testbenches, including object-oriented, constrained-random stimulus and functional coverage capabilities. VCS’ industry leading constraint solver technology is powered by multiple solver engines that simultaneously analyze all user specified constraints to rapidly generate high-quality random stimulus to verify the design for corner case behavior. These engines will find a solution to user constraints, if one exists, minimizing constraint conflicts and maximizing verification productivity.

Figure 1: Multicore support

Complete assertion technologies
The native assertion technology in the VCS solution enables an efficient methodology for deploying designfor- verification (DVF) techniques. The built-in support of SystemVerilog and OpenVera assertions allows designers to easily adopt DFV and find more bugs quickly. A rich assertion-checker library and a unique library of Assertion IP make it even easier to deploy assertions across teams and improve their verification quality. The assertions serve the needs of simulation as well as formal property verification environment.

Comprehensive coverage
The VCS solution provides highperformance, built-in coverage technology to measure verification completeness. Echo testbench coverage convergence technology reduces the time it takes to reach full stimulus functional coverage. Comprehensive coverage includes code coverage, functional coverage and assertion coverage. Unified coverage aggregates all aspects of coverage in a common database, thereby allowing powerful queries and useful unified report generation. The unified coverage database offers 2x to 5x improvement in merge times and up to 2x reduction in disk space usage, which is useful for large regression environments.

Figure 2: Unified coverage

Figure 3: Discovery Visualization Environment (DVE)

Advanced debugging and visualization environment
The VCS solution includes the Discovery Visualization Environment (DVE), a next-generation, full-featured debug and visualization environment. The DVE has been specifically architected to work with all of the advanced bugfinding technology in VCS and shares a common look and feel with other Synopsys graphical-based analysis tools. DVE enables easy access to design and verification data along with an intuitive drag-and-drop or menu-and-icon driven environment. Transaction-level debug is seamlessly integrated into DVE, allowing users to analyze and debug transactions in both list view and waveform view. Its debug capabilities include: tracing drivers, waveform compare, schematic views, path schematics and support for the highly efficient Synopsys compact VCD+ binary dump format. It also provides elegant mixed-HDL (SystemVerilog, VHDL and Verilog) and SystemC/C++ language debugging windows along with next-generation assertion tracing capabilities that help automate the manual tracing of relevant signals and sequences. TCL support is provided for interaction or batch control and skin/menu customization. A unified command language is supported to provide a common set of commands for all tools, languages and environments, making it easy to deploy new technology across design teams.

Verification methodology
The VCS solution’s powerful testbench engines are complemented by the proven VMM methodology, defined in the popular Verification Methodology Manual for SystemVerilog, and layered testbench architecture that enables both new and experienced verification engineers to quickly create and deploy advanced, reusable, efficient verification environments. This methodology, developed and used by verification experts, helps users adopt industry-best practices to get the best possible results from the VCS solution. In addition, the VMM methodology provides a number of applications, such as Register Abstraction Layer (RAL) and others, to cut down on the time taken to set up a powerful verification environment. All the VMM applications, a detailed reference manual and examples are provided with the VCS solution. The VCS Verification Library provides extensive support for the VMM methodology, including an object interface and scenario generators. VCS also supports Accellera Universal Verification Methodology (UVM) base classes and the VMM/UVM interoperability kit, which enables the use of VMM with UVM.