About a year ago, Synopsys announced a corporate initiative to take advantage of multicore processor technology across its broad tool portfolio. On the verification front, the first tool out of the multicore gate was HSPICE, with impressive performance gains.
Tom Borgstrom

In SystemVerilog, unlike C, you don’t have to explictly free dynamically allocated class instances. Like most modern programming languages, SystemVerilog includes a garbage collector that frees memory that is no longer needed.
Janick Bergeron, Design Entomologist

Hello, everyone interested in EDA interoperability and fans of The Standards Game. I’d like to invite you to join me at the 21st Synopsys EDA Interoperability Forum, sponsored by Sun Microsystems.
Karen Bartleson

Well, who doesn’t believe in coincidence? First, I meet with CriticalBlue’s Skip Hovsmith and we have a interesting discussion about multi core software development practices (or lack thereof) and on the same day I run across Glenn Perry’s article
Frank Schirrmeister

The Verilog-AMS Technical Subcommittee of Accellera held another in a series of conference call discussions on Tuesday Oct-7, to further explore the topic of AMS Assertions.
Mike Demler