Equivalence checking of low-power and multi-voltage designs can be quite challenging. These designs require specification of the low-power behavior and structures necessary to create an operational design.
Robert Hatt Formality CAE Synopsys

Formality is an equivalence-checking solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. Formality delivers superior completion on designs compiled with DC Ultra.
Erin Hatch Formality CAE, Synopsys

Today’s complex SoC designs present many verification challenges for design teams. Historically, to ensure design integrity throughout the implementation process, engineers used a bottom-up, hierarchical equivalence checking methodology to reduce the size and complexity of the verification.
Formality Hier-IQ

An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified.
Demos Anastasakis, Robert Damiano, Hi-Keung Tony Ma, Ted Stanion

This paper discusses the available methodologies for verifying arithmetic designs, the strengths and weaknesses of available approaches, and Formality's new methodology to greatly improve the coverage and performance of arithmetic verification.
Mark Patton, Formality Product Manager, Synopsys, Mitchell Mliner, R&D Group Director, Synopsys

Equivalency checking is an important and necessary step to verify the functional correctness of a design’s implementation. However, conducting retiming during design implementation often made functional verification impossible.
Mark Patton, Formality Product Manager, Synopsys, Mike Tarsi, Formality Engineering Manager

Have you ever experienced the "now what" anxiety that accompanies a failing equivalence checking verification? Have you found yourself staring at a logic cone with thousands of gates and no clear place to start the debug process?
Mark Patton, Product Manager

It can be very challenging to functionally verify a design that has undergone significant transformations during implementation. This paper discusses the use of setup guidance to simplify the equivalence-checking (EC) process.
Marl Patton, Formality Product Manager, Synopsys, John Lehman, Formality Applications Engineering Manager, Synopsys.