| Efficient & Accurate Memory Timing & Power Analysis using CustomSim |
With the growing complexity of device models and the increasing impact on timing and power measurements from physical layout effects, accurate memory verification within a reasonable timeframe is a necessity. This webinar highlihgts memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time. Learn how Synopsys’ CustomSim™ solution is being used today for accurate and efficient memory timing and power analysis.
Bradley Geden, Product Marketing Manager
Dec 15, 2009 |
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| Galaxy Custom Designer--A Complete Custom Implementation Flow |
Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, and Chris Shaw, Technical Marketing Manager
Nov 03, 2009 |
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| HSPICE and Custom Designer—Modern-era Analog and RF Circuit Design |
Analog/RF design solution helps meet design challenges
Christopher Labrecque, HSPICE Marketing Manager, and Fredrik Ivarsson, Custom Design Corporate Applications Engineer
Oct 04, 2009 |
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| Extraction Techniques to Accelerate High-Capacity Simulation |
Star-RCXT™ provides unique gate-level extraction techniques to address productivity bottlenecks in physical implementation and signoff. Our experts demonstrate how the latest process modeling and extraction features can help you achieve accurate and faster signoff.
Krishnakumar Sundaresan, Principal Engineer at Synopsys; Hong Liu, CAE for extraction products at Synopsys
Jul 21, 2009 |
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| Increase Design Confidence with CustomSim |
In this webinar you will learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement.
Synopsys
Apr 28, 2009 |
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| Get the Most Out of Your HSPICE |
Over the past few years, Synopsys has sped up HSPICE, achieving industry leading performance while maintaining HSPICE’s “signoff quality” simulation accuracy.
Dr. Kishore Singhal, Synopsys Scientist, Dr. Scott Wedge, Sr. Staff Engineer, Ted Mido, Sr. Staff Engineer, Harald Von Sosen – Principle Engineer
Oct 13, 2008 |
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| Feb 23 Webcast Robust SI Analysis of a DDR2 Interface with HSPICE |
For years designers around the world have trusted HSPICE for their signal integrity simulation needs. For video memory and many other applications, increases in chip and board speeds over the last few years have created significant and widespread demand for accurate signal integrity analysis. This tutorial walks through the setup, simulation and analysis of a Synopsys DDR2 memory interface highlighting HSPICE’s signal integrity analysis features.
Dr. Scott Wedge Senior Staff Engineer, Synopsys
Ted Mido Senior Staff Engineer
Feb 13, 2007 |
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| Predicting PLL Phase Noise & Jitter with HSPICE RF |
Due to today’s ever increasing data rates, phase noise and jitter specifications are now critical aspects of modern phase-locked loop design.
Dr. Scott Wedge Senior Staff Engineer, Synopsys
Jan 23, 2007 |
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| Nov.7 Archived Webcast HSIMplus – Beyond FAST Spice Simulation – Listen Now! |
Fast-SPICE simulation in the past was limited primarily to functional verification, because the gains achieved in simulation performance required giving up on SPICE accuracy.
Mike Demler
Cheryl Ajluni
Giuseppe Oliva
Nov 07, 2006 |
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| Faster Verification Performance with VCS Native Testbench and RVM |
The Native Testbench feature of Synopsys' VCS comprehensive RTL verification solution enables both design and advanced testbench to be compiled together for up to 5x faster verification performance.
Synopsys, Inc.
Mar 30, 2005 |
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| Static Verification with LEDA in Discovery Verification Platform |
Come join us for a one-hour live webcast to see how Synopsys addresses these design verification problems with LEDA, a programmable mixed language RTL and gate design checker in the Discovery Verification platform.
Synopsys Inc.;
Aug 13, 2003 |
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| Introduction to SystemVerilog |
With designs continuing to increase in size and complexity, today's design and verification methodologies are being stressed to the breaking point.
Synopsys inc.;
Oct 17, 2002 |
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| Introduction to Assertion-Based Verification |
Ever increasing design size and complexity are stressing current verification methodologies.
Synopsys inc.;
Aug 13, 2002 |
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