HSIM^plus Post-layout Analysis
In order to reduce the risk of expensive mask changes and silicon re-spins; the signoff process for today's designs must account for the impact of parasitic devices on timing, power and reliability. These effects can only be accurately analyzed post-layout, by extraction and back-annotation of potentially tens or hundreds of millions of elements, which can easily exceed the capacity of competitor's Fast SPICE simulators. By exploiting the hierarchical architecture of the HSIM core simulator, HSIM^plus provides a complete set of tools for analyzing the impact of IR drop in power and ground busses, coupling effects in signal interconnect, and potential reliability failures from electro-migration.

• HSIM^plus PLX: Post-Layout Acceleration
• HSIM^plus PWRA: Power Net Reliability Analysis
• HSIM^plus SPRES: Static Power Net Resistance
• HSIM^plus SIGRA: Signal Net Reliability

HSIM^plus MOSRA: MOS Reliability Analysis
Fragile nanometer transistors are stressed by high field strengths in the device channel, by high temperature, and by high-frequency switching activity over extended periods of time. These stress effects lead to device 'aging', resulting in performance degradation and designs that fail to meet specification during their expected operating life. HSIM^plus MOSRA allows users to add aging effects to industry-standard BSIM3 and BSIM4 models. MOSRA enables users to measure performance degradation over time, by comparing the results of pre-stress and post-stress simulation results.

• HSIM^plus MOSFET Reliability

Hierarchical Back-Annotation
The proprietary technology in HSIMplus PLX provides Hierarchical Back-Annotation (HBA) that can maintain pre-layout hierarchy in the presence of a flat parasitic database. By retaining as much as possible of the pre-layout hierarchy, post-layout simulation capacity and performance are improved.

Figure 1. Back-annotation with PLX

Structural Back-Annotation
It is common in custom IC design to have a mismatch between the representation of a circuit in pre-layout schematics, and the physical design of a functionally-equivalent circuit in the layout. Examples where structural mismatch occurs are splitting devices into parallel fingers - introducing new nodes and elements, and re-ordering of a stack of series transistors that alters connectivity.

Figure 2. Re-ordering of devices in layout

HSIM^plus SPRES: Static Power Net Resistance
Before performing a complete dynamic simulation for measurement of IR drop effects, a quick DC analysis of power and ground bus resistance can be used to catch gross errors such as missing vias and undersized metallization. The HSIM^plus SPRES option determines the resistance from each external power pad connection to the power pins of internal blocks, generating text reports and GDSII resistance maps for graphical visualization of power and ground bus resistance through all metal and via layers.

HSIM^plus PWRA: Power Net Reliability Analysis
The HSIM^plus PWRA option adds to HSIM the capability for analysis of IR drop and electro-migration in power and ground busses, while simultaneously accounting for the effects of interconnect resistance on dynamic circuit performance. The unique direct-coupled methodology in PWRA provides highly accurate measurement of power bus currents, by performing full circuit simulation in the presence of back-annotated parasitics. PWRA overcomes the limitations of simulation with millions of extracted parasitic resistors, by incorporating built-in compression and reduction algorithms to maintain accuracy, capacity and performance.

In the proprietary HSIM^plus methodology accurate transient current waveforms are acquired during dynamic simulation, and are used for detailed measurement of IR drop and current density in the complete, un-reduced power and ground nets. Other less-accurate approaches to power-net analysis estimate IR drop by characterizing cells before they are placed into a circuit layout, where the true in-silicon effects will be seen. Graphical output from PWRA in GDSII and other formats allows designers to overlay results on their layout design for analysis and debug. When used in conjunction with HSIM^plus PLX, a complete flow for transistor-level analysis of IR drop and electro-migration is available with the capacity to large nanometer designs.

HSIM^plus SIGRA: Signal Net Reliability
The SIGRA option calculates current densities in narrow signal nets, to determine their susceptibility to electro-migration. Bi-directional current flow is correctly considered, including calculation of the RMS currents required for monitoring Joule heating within the design. These results are presented as GDSII files for physical visualization, complementing the PWRA option. When used in conjunction with PLX, SIGRA can include all of the design's extracted coupling capacitors in addition to the grounded capacitors. This provides a high level of precision in determining the current entering or leaving segments of signal net interconnect, enhancing the quality of results available to designers