Overview
NanoSim™ is the cornerstone of Synopsys’ comprehensive mixed-signal verification solution, Discovery AMS. NanoSim is an advanced transistor-level circuit simulation and analysis tool for analog, digital and mixed-signal design verification. It is a robust and easy to use solution, with very high simulation throughput and capacity for multi-million transistor SoC’s and accuracy for designs at 90 nanometer and below.

Key Benefits

• Provides high accuracy for designs at 90 nanometer and below
• Simulation speeds up to orders of magnitude faster than SPICE
• Capacity to simulate large memory and SoC designs, e.g. 512 Mb DRAM with 1 Billion elements
• Provides flexibility to trade-off accuracy versus performance
• Seamless integration with parasitic extraction tool, Star-RCXT for efficient post-layout simulation
• Fits in any methodology with its support for all major SPICE netlist and model formats
• Ease of adoption using intuitive GUI based setup and simulation environment
• Boosts productivity with comprehensive built-in timing and power diagnostic functions

Figure 1. NanoSim Flow Diagram

Table 1. NanoSim Benchmark Data

NanoSim Technology: Accuracy, Performance & Capacity Leader
NanoSim combines best-in-class simulation technologies from TimeMill® and PowerMill® to deliver combined timing and power analysis and diagnostics in a single tool. It is a completely backward compatible solution with TimeMill/PowerMill, accepting the same netlist and setup, with the quality of results guaranteed to be the same.

Some key aspects of NanoSim proprietary technology are:

• Intelligent partitioning and synchronization of design parallelizes computations
• Combination of event- and time- based simulation delivers speed without sacrificing accuracy
• Automatic topology detection and application of optimal simulation mode
• Uses same device models similar as HSPICE assuring high accuracy
• Accurate modeling of DSM effects such voltage dependent Miller terms, crosstalk analysis and ground bounce effects
• Simulation modes ranging from PWL for digital circuits to SPICE like Analytic mode
• Direct read of parasitic data in DSPF or SPEF formats
• Advanced RC compaction algorithm, LNS that maintains network passivity and preserves coupling capacitance providing high performance for post-layout designs

NanoSim supports:

• Netlist Input: SPICE, Verilog, EDIF, LSIM, SPF, SPEF
• Stimulus: .vec, Verilog HDL testbenches (VCS required)
• Models: BJTs, BSIM3.x, BSIM 4.x MM905, JFET, MESFET, HVMOS*, SiGe VBIC, SOI, etc.
• Use of pre-characterized technology files for faster run times
• Output: .out, turboWave .fsdb and API for custom output into other display tools.

Verifying Billion-element Memory Designs with NanoSim
NanoSim uses an innovative Hierarchical Reduction Algorithm (HAR) to provide the capacity for verifying large memory designs. This algorithm uses a combination of hierarchical database and simulation approach to automatically identify and reduce the active memory portions. Figure 2 shows some examples of the simulation results achieved using this algorithm.

Figure 2. HAR Performance Table

Figure 3. NanoSim Workbench GUI

Mixed-Signal SoC Design Verification Solution
NanoSim provides a comprehensive SoC verification solution with the flexibility to simulate designs in any combination of Verilog, Verilog-A, VHDL, SPICE and C. This is based on a direct kernel integration with VCS and built-in support for high-level analog behavioral modeling languages — IEEE 1364 standard Verilog-A and the proprietary C-based Analog Digital Functional Modeling Interface (ADFMI).

The key benefits of this solution are:

• Flexibility to combine gate level performance with transistor level accuracy in any mixture of behavioral, RTL or gate modules and custom analog or digital transistor blocks
• Up to 100x speed-up in simulation through-put by simulating at higher abstraction
• Early verification of digital and analog interaction enables better architecture and IP selection
• Plug and play solution allows direct instantiation of blocks with no netlist changes
• Integrated solution to display simulation results from NanoSim and VCS in a unified manner
• Leverage analog behavioral modeling in Verilog-A and C for top-down, design verification
• Easily import and verify embedded IP, e.g. Verilog IP with a SPICE netlist or vice versa.

*VCS license is required (purchased separately)

Design Debugging and Analysis
NanoSim has a rich set of diagnostics and interactive debug features that help a user quickly identify and isolate problems. Some of these are:

• Function checks:
• Node toggles, unsettled/ indeterminate/tri-state/unknown nodes, out-of-range voltage swings on nodes and elements
• Full-chip, block-level and node-level analysis
• Average, RMS, peak and instantaneous currents
• Hierarchical current and power reporting
• Power analysis
• Dynamic: detection of hot spots, DC leakage paths, excessive current, fast transitioning nodes
• Static: detection of short-circuit paths, maximum rise/fall times
• Power budgeting: average, RMS, peak and instantaneous currents at block and chip-level
• Timing
• Dynamic: timing checks include setup, hold, pulse-width, edge-to-edge

Plug-and-Play Solution
NanoSim provides a plug and play solution, not only with its wide ranging support for various netlist and models, but also with various ease of use features, that makes adoption into any flow a breeze:

• Intuitive GUI-based workbench (see Figure 3)
• Facilitates optimal simulation setup without learning the commands decreasing ramp-up time
• Hierarchy explorer gives graphical view of complicated netlist
• Configuration wizard enables simulation setup based on design type
• Run simulation within the GUI or in batch mode
• Simulation speed and accuracy trade-off with single command
• Save/Restore capability to help speed up multiple simulation runs
• Interactive mode debug capability
• Tcl command-line interface with support for scripting for simulation output customization
• Custom output generation capability to interface with any third-party waveform tool

Third Party Tool Support

• Cadence Analog Design Environment (Analog Artist): Direct integration using OASIS
• TurboWave: Waveform Viewer

Options
Block Delay Calculator (BDC)
BDC is an option to NanoSim that helps designers do timing characterization, which is useful for memory designers who need timing models for embedded applications. Using BDC commands, designers can automatically generate models for Setup/Hold timing and pin-to-pin delays in SDF and PathMill® black-box formats. BDC helps designers achieve timing convergence for verification of the design.

Platform Support and Availability
NanoSim is available electronically or on CD-ROM, and fully supports the following platforms:

• Solaris 7 and 8, both 32-bit and 64-bit
• HP 11.00, both 32-bit and 64-bit
• IBM 4.3.3 (32-bit only)
• Linux 32-bit and 64-bit (IPF)