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Blogs
Blogs
All Synopsys Blogs
Analog Insights
Technical content and latest trends about AMS, from Analog to Mixed-signal and RF
Hélène Thibiéroz
A View from the Top: A System-Level Blog
Shift towards adoption of virtual platforms and ESL technologies.
Achim Nohl
On Verification: Software-to-Silicon
Exploring software-to-silicon verification.
Tom Borgstrom
The Standards Game
Observation, information and experiences with technical standards.
Karen Bartleson
Verification Martial Arts
Technical information and tutorials focusing on functional verification.
Janick Bergeron
All Synopsys Blogs
HSPICE SIG VIDEOLOG
HSPICE: Tackling Design Integrity of Multi-Gbps Systems
HSPICE TIPS WEBINAR
Reduce simulation time without compromising HSPICE gold-standard accuracy
HSPICE MINI DEMOS
See how HPP technology and StatEye analysis can speed up simulation of analog circuits!
HSPICE HPP WEBINAR
Accelerate analog simulation with HSPICE Precision Parallel technology
News
BiTMICRO Selects Synopsys for Chip Design Automation
Synopsys Collaborates with Sigrity to Accelerate Signal Integrity Analysis
eSilicon Selects Synopsys' Custom IC Design Solution and Tapes Out 28-nm Designs
Synopsys and GLOBALFOUNDRIES Collaborate to Deliver 65nm iPDKs
Synopsys Custom Design Solution Enables Moortec Semiconductor to Tape Out....
Synopsys and TSMC Collaborate to Deliver Custom Design Solution for 28nm....
Synopsys Mixed-signal Verification Solution Delivers 5X Speed-up at Amlogic
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All Synopsys News
Articles
How VHDL designers can exploit SystemVerilog
Synopsys tries to organize its efforts in EDA multiprocessing
Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli
VMM application packages- the next level of productivity
IC verification key: ‘Do it step by step, don’t cut corners’
Nightmares in Functional Verification
Future Verification Appears Uncertain
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Blogs
Analog Insights
A View from the Top: A System-Level Blog
On Verification: Software-to-Silicon
The Standards Game
Verification Martial Arts
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Success Stories
Etron Achieves First-Silicon Success of USB3.0 SoC Using Synopsys Proven Solutions
HSPICE-Quotes
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White Papers
Custom and Mixed-Signal Design Solution
MOS Device Aging Analysis with HSPICE and CustomSim
De-risking Variation-aware Custom IC Design with Solido Variation Designer and Synopsys HSPICE
Accelerating Analog Simulation with HSPICE Precision Parallel Technology
PLL Noise Analysis with HSPICE RF
HSPICE Testbench Technologies for Analog & RFIC Design
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Webinars
Get the Most from Your HSPICE Simulation
Avoid EM & IR-drop Effects in Custom IP Blocks
Regression and Analysis for Mixed-Signal Verification
Jitter Analysis Using HSPICE Transient Noise Techniques
Mixed-Signal Design Verification Techniques
Advances in Circuit Analysis with Custom Designer SAE
Accelerate Analog Simulation with HSPICE
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Videos
2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems
Introducing HSPICE Precision Parallel Technology
DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification
HSPICE SIG: A Converging Analog World: Silicon, Package and System
HSPICE Mini Demos
IMS MicroApp Video: Causality Considerations for Multi-Gigabit StatEye Analysis
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Training Courses
HSPICE Essentials
NanoSim
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WHAT’S NEW IN HSPICE
HSPICE Integrator Program
Signal Integrity Users Forum
Device Models Supported
Download Verilog-A Models
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