Overview
Discovery AMS provides a comprehensive environment that enables verification of full-chip mixed-signal designs with built-in support for Verilog-AMS language defined by the Accellera 2.0 standard. It provides a unique combination of accuracy, performance and capacity with the flexibility of simulating design abstractions in any combination of Verilog, VHDL, SPICE, Verilog-A and Verilog-AMS.
HSIMplus HDL Co-Simulation
FastSPICE co-simulation with Synopsys VCS enables verification of designs that consist of a combination of SPICE transistor-level circuit netlists and Verilog or VHDL gate or RTL-level digital modules. The direct kernel integration (DKI) of Synopsys’ industry-leading FastSPICE solutions (HSIM, Nanosim, and XA) with digital simulation in Synopsys VCS, enables designers to perform comprehensive mixed-signal analysis to gain a full chip view of complex SoC designs. Logic and circuit designs are often performed by different teams, using different database formats and languages. FastSPICE co-simulation connects digital and analog design flows to enhance simulation performance and verification coverage for large mixed-signal circuits.