| Simulation of Advanced Semiconductor Devices |
This webinar will discuss the application of TCAD to high-k/metal-gate transistors and 3-D modeling FinFET devices, focusing on the physical models and 3-D modeling techniques required to achieve successful simulations.
Synopsys
Dec 01, 2009 |
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| Introduction to TCAD Sentaurus New Release Features |
This webinar will unveil the new features in the Synopsys TCAD Sentaurus June 2009 release.
Synopsys Events
Jul 22, 2009 |
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| Simulation of Multi-Junction Solar Cells Using TCAD Sentaurus |
This webinar will address the design and optimization of multi-junction solar cells using the TCAD Sentaurus tools from Synopsys.
Synopsys events
Mar 16, 2009 |
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| Thermo Mechanical Finite Element Analysis of 3D Through-silicon Via (TSV) Structures |
3D integration, where multiple die are stacked and interconnected in the vertical dimension using through-silicon vias (TSVs), is considered by many to offer significant performance and cost benefits for key applications.
Synopsys Events
Jan 28, 2009 |
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| CMOS Flow from Process to Device to Yield Management with Process Compact Models (PCMs) |
Yield and performance are the foremost concerns for device design in the semiconductor industry, and a clear understanding of their sensitivity to process parameters is key for better control.
Synopsys Events
Nov 12, 2008 |
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| Addressing the Challenges in EUV Lithography by Simulation |
EUV lithography is considered the most viable solution for printing the critical features related to the 22nm technology node.
Synopsys Events
Sep 01, 2008 |
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| Thin Film Solar Cell Simulation |
Thin film solar cells are currently the focus of worldwide research and development efforts aimed at bringing to market more efficient and cost effective processes and designs.
Synopsys Events
Aug 01, 2008 |
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| Simulation of SiC Devices – Models and Techniques |
Silicon carbide (SiC) has long been recognized as a promising semiconductor for power electronics in view of its superior material attributes, allowing the realization of higher blocking voltages and switching frequencies.
Synopsys Events
Jul 01, 2008 |
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| 3D Process and Device Simulation - Practical Guidelines |
The rising complexity in the processing steps and device structures of semiconductor technologies is leading to a corresponding rise in 3D effects which must be analyzed with simulation.
Synopsys Events
Jun 01, 2008 |
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| Modeling Non-volatile Memory Technologies with Sentaurus TCAD |
The spread of non-volatile memory devices has been phenomenal in recent years, and is fast replacing hard drives in terms of memory capacity and challenging DRAMs high speed capability. A new generation of non-volatile memory devices have kept scientists and designers busy researching and optimizing designs like SONOS memory, new materials like chalcogenide (GST) for Phase Change Memory, or means to pump charge into Nano Crystals to store information.
Synopsys Events
May 01, 2008 |
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| Resist Modeling with Sentaurus Lithography |
This webcast will provide an introduction to lithography simulation and will demonstrate the benefits of Synopsys TCAD Sentaurus Lithography using application examples. With Sentaurus Lithography, advanced lithography process simulation joins the physics-oriented technology simulation product family, TCAD Sentaurus.
Synopsys Events
Apr 01, 2008 |
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| Electromagnetic Simulation of Image Sensors: From Design to Manufacturability |
In back end of line (BEoL) processing, high mechanical stresses and large stress gradients in local regions of interconnect structures can lead to yield loss and reliability failures.
Synopsys Events
Mar 01, 2008 |
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| Gallium Nitride HFETs: Physical Models and Simulations for RF and Power Applications |
In back end of line (BEoL) processing, high mechanical stresses and large stress gradients in local regions of interconnect structures can lead to yield loss and reliability failures.
Synopsys Events
Feb 01, 2008 |
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| Process and Stress Simulation for BEoL Reliability and Mobility Enhancement |
In back end of line (BEoL) processing, high mechanical stresses and large stress gradients in local regions of interconnect structures can lead to yield loss and reliability failures.
Synopsys Events
Jan 01, 2008 |
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