Overview
The economic advantages stemming from increasing transistor density and performance in CMOS provide the impetus to today’s 45nm and future scaled technologies; however, device scaling requires new approaches to control gate leakage and short-channel effects. High-k gate dieletrics, in combination with metal gates, have emerged as a key process module to address these challenges, while FinFETs loom on the technology horizon as evolutionary alternatives to today’s planar MOSFETs.

This webinar will discuss the application of TCAD to high-k/metal-gate transistors and 3-D modeling FinFET devices, focusing on the physical models and 3-D modeling techniques required to achieve successful simulations.

Who Should Attend?
This webinar is intended for technology development engineers and managers, reliability engineers, process integration engineers, and research scientists.

View the Recording