Applications

If you are interested in accessing any ot the TCAD Application Examples, please fill out the sample request form and you will be emailed download instructions.

CMOS Devices

Sentaurus Technology Template: CMOS Processing

The process flow represents a generic 90 nm technology node and is intended to serve as a convenient starting point for any deep submicron CMOS simulation project.

Sentaurus Technology Template: CMOS Characterization

This Sentaurus TCAD simulation project provides a template setup for farsubmicron CMOS device characterization. IdVgs curves for a low drain bias and high drain bias are simulated for NMOS and PMOS structures with various gate lengths.

Sentaurus Technology Template: Process Emulation of 3D NMOS

This Sentaurus TCAD simulation project provides a template setup for the process emulation of a deep submicron 3D NMOS transistor.

Advanced Examples (2D)

Process and Device Simulations of Partially Depleted SOI CMOS Devices with TCAD Sentaurus

Partially depleted silicon-on-insulator (PDSOI) transistors are widely used for high-performance VLSI CMOS, because of significantly reduced junction capacitances and an increased speed compared with bulk silicon MOSFETs.

Simulation of CMOS Device Using Selective Epitaxial Growth Isolation and Hybrid Orientation Technique

Compared to (100) substrates the hole mobility is much higher in MOSFETs fabricated on (110) or (111) substrates with conventional SiO2, as the highest piezoresistance coefficient is obtained on the (110) surface under compressive stress.

Simulations of Strained-Silicon CMOS Devices

Synopsys TCAD has all of the models required to perform process as well as device simulations of modern strained-silicon and silicon-germanium devices.

Simulation of Laser/Flash Annealing with Sentaurus Process

This example provides a template for conducting laser annealing simulations in Sentaurus Process.

Sentaurus Process Simulation of a 30 nm Gate-length NMOS Transistor with Hybrid Continuum and Atomistic Diffusions

This application example shows the process simulation of a 30-nm gate-length NMOS flow in Sentaurus Process using a combined approach of both continuum (five-stream) and atomistic (kinetic Monte Carlo) diffusions.

Simulation of CMOS Degradation Kinetics with TCAD Sentaurus

Trap formation kinetics in the channel of an NMOSFET is simulated in this TCAD Sentaurus project.

Simulation of Scanning Laser Annealing in Sentaurus Process

Shallow junctions with low sheet resistance are required for future generation short channel devices.

Advanced Examples (3D)

Process and Device Simulations of Trench Capacitor Embedded 70 nm DRAM

This application note showcases the TCAD Sentaurus 3D simulation capabilites for a trench capacitor embedded 3D DRAM cell.

Tri-gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

A tri-gate bulk MOSFET design utilizing a low aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap.

Modeling of CMOS Image Sensor

As the device dimensions continue to scale down, simulations become more and more important in the design process allowing for reduced costs and time savings during the development cycle. Modeling of a CMOS image sensor (CIS) is a particularly challenging task which often requires a full three-dimensional approach.

Three-dimensional Simulations of Twin Silicon Nanowire NMOS Transistor

Modern semiconductor industry is facing numerous challenges as the next generation of devices are developed and manufactured.

Three-dimensional Simulation of NMOS Transistor

This project demonstrates three-dimensional simulations of an NMOS transistor including both the process and device parts. The process simulation part is performed using the 3D process simulator Sentaurus Process and the structure editor Sentaurus Structure Editor.

Three-dimensional Simulations of Strained-Silicon CMOS Devices

To demonstrate the three-dimensional capabilities of TCAD Sentaurus for strained silicon, both full process and device 3D simulations for typical strained-silicon CMOS devices are presented.

25 nm Omega FinFET: Three-dimensional Process and Device Simulations

This Sentaurus TCAD simulation project provides a template setup for three-dimensional process simulation and device simulations of Omega FinFETs.

Advanced Examples

Simulation of Current Filament During Electrostatic Discharge Pulse

This project demonstrates a transmission line pulse (TLP) simulation of a three-dimensional bipolar structure.

Bipolar Technologies

Sentaurus Technology Template: SiGe HBT Processing

Synopsys TCAD offers an extensive array of physical models to simulate silicon-germanium devices at both process and device simulation levels, including extraction of key device performance parameters.

Sentaurus Technology Template: Characterization of Bipolar Transistors

This Sentaurus TCAD simulation project provides a template setup for the characterization of bipolar transistors.

Power Devices

Simulation of 4H-SiC Vertical Junction FET in Sentaurus Device

Silicon carbide (SiC) has long been recognized as a superior semiconductor for high-power and high-temperature applications in view of its high breakdown electric field and excellent thermal conductivity. Since the pioneering work of Tairov and Tsvetkov who developed the modified seed sublimation growth process that spearheaded today's SiC substrate technology, the industry has improved steadily the quality, size, and cost of SiC substrates, all of which are key manufacturability considerations in any semiconductor technology.

Sentaurus Technology Template: LDMOS Processing

This Sentaurus TCAD simulation project provides a template setup for laterally diffused MOS (LDMOS) process simulations.

Sentaurus Technology Template: IGBT Characterization

This Sentaurus TCAD simulation project provides a template setup for IGBT device characterization.

Sentaurus Technology Template: SiC Schottky Diode

This Sentaurus TCAD simulation project provides a template setup for the simulation of silicon-carbide devices.