| NVIDIA licenses Synopsys' yield management tool |
Graphics chip vendor NVIDIA Corp. has licensed Synopsys' Yield Explorer, a yield management tool said to expedite the discovery and mitigation of yield limiters in leading-edge ICs, to reduce time-to-volume.
Oct 28, 2009 |
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| EDN: Design-centric yield management |
In the race to the market, IC vendors have few avenues remaining to claim the first-to-market advantage.
Mar 12, 2009 |
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| EDN: Synopsys tries to organize its efforts in EDA multiprocessing |
It’s hard to imagine a set of applications that need computing resources more than the chain of EDA tools for a 65 nm chip design. (OK, searching for extraterrestrials, maybe, but the economics are a bit different there.)
Mar 10, 2008 |
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| SCDsource: Synopsys pledges multicore support for EDA applications |
Responding to one of the key challenges facing established EDA vendors, Synopsys this week (March 10) is announcing a "multicore initiative" to re-architect its most commonly-used IC design and verification products to run on multicore platforms.
Mar 10, 2008 |
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| Semiconductor International: Nikon and Synopsys deliver on Advanced OPC promise |
The latest release of Synopsys's Proteus optical proximity correction (OPC) software now incorporates proprietary data from Nikon's lithography exposure tools.
Oct 13, 2007 |
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| Chip Design: EDA Is Stepping Up to Meet New DFM Demands |
"Smaller, faster, and cheaper” has been the mantra of the semiconductor industry for over 40 years. But the latest 45- and 32-nm technology nodes have many in the semiconductor industry crying “uncle.”
Oct 13, 2007 |
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 A New Approach to Higher Yielding Silicon |
The production of leading edge semiconductors relies on a delicate balance between design and manufacturing.
Apr 01, 2007 |
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| Yield Analysis and Optimization Ensures Tight Design-to-Manufacturing Links |
DFM Drives New Business Models For Design Automation DFM — What Can Designers Do?
Mar 24, 2007 |
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| Model-Based Metal Fill Optimizes Planarization and Increases Yield |
Copper interconnect was introduced to the mainstream at 130nm because of its significant advantages compared to aluminum, such as reduction in resistivity and power consumption and resistance to electromigration.
Mar 22, 2007 |
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| Improving 90nm FPGA chips with an alternating phase-shift mask |
Existing nonphase-compliant chip designs can be made using a dark field alternating phase shift gate mask if proper EDA steps are taken. Gate width and line-end shortening are both reduced, improving yield and performance.
Nov 01, 2006 |
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| DFM Takes on Process Variability |
Through a variety of products, some specific to the chemical mechanical planarization (CMP) process, others to lithography, EDA suppliers have begun addressing process variability.
Nov 01, 2006 |
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| DFM In Action |
In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node.
Dec 01, 2005 |
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| Spread of RET masks at 65nm node drives 'virtual stepper' software |
Next-generation reticle sets for 65nm ICs will be blanketed with resolution enhancement technology (RET) so that current-generation lithography tools can adequately pattern devices and interconnects on production wafers.
Sep 01, 2004 |
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| EE Times: Synopsys CEO calls for DFM cooperation |
Aart de Geus has added his influential voice to the design-for-manufacturing discourse.
Jul 26, 2004 |
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| Solid State Technology: Analyzing strained-silicon options for stress-engineering transistors |
Future silicon technology will depend on locally strained silicon channels to squeeze higher currents from each process node.
Jul 01, 2004 |
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