ESP-CV is a tool designed to perform functional equivalence checks between two different design representations. The new power intent verification features in ESP-CV provide the ability to verify various types of power management circuitry used in low power designs. These designs may be described as Verilog behavioral models, RTL, gates, transistors, or a SPICE netlist.
Clay McDonald, R&D Manager, Implementation Group, Synopsys; Dave Hedges, CAE, Implementation Group, Synopsys
Sep 15, 2010

Increasing design complexity and the impact of new parasitic effects make accuracy and productivity for IC design and signoff analysis even more challenging beyond the 28nm process node. In this webinar, Synopsys experts will discuss how StarRC addresses these advanced challenges at 28nm through silicon-accurate modeling and high-performance extraction, enabling SoC designers to achieve signoff with increased confidence.
Krishnakumar Sundaresan, CAE, Synopsys
Sep 14, 2010

This technical webinar will explain how PrimeTime PX can be used to analyze the effectiveness of low power design techniques such as clock gating, use of multi-voltage rails and power gating. Attendees will learn how to further optimize their designs for power by analyzing which low-power techniques work best under differing conditions. You will also learn how to use PrimeTime PX to understand which modes of operation consume the most power.
David Le, Senior Manager, CAE, Implementation Group, Synopsys; Maria Tovey, Staff Engineer, CAE, Implementation Group, Synopsys
Aug 03, 2010

This technical webinar will describe how easily you can access the embedded Rapid3D technology in StarRC Custom using existing interfaces and setup to drive high accuracy extraction for multiple design applications. Our experts will explain the latest field solver advancements in Rapid3D that deliver the high performance, capacity and near-linear multicore scalability, enabling you to apply the technology on designs consisting of tens to one hundreds of thousands of nets.
Omar Shah, Staff Engineer, CAE / Extraction, Synopsys
Jul 27, 2010

This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010

NanoTime is the next-generation transistor-level static timing analysis solution that addresses the challenge of signal integrity (SI) analysis with custom designs. The advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design cycle to avoid expensive silicon re-spins. Its seamless integration with Custom Designer provide users with additional productivity improvement such as configuration setup, timing reports with cross probing between schematic and layout and library model generation all within the Custom Designer environment.
Darryl Eng, Sr. CAE Manager, Implementation Group, Synopsys; Les Spruiell, Senior Manager, Product Marketing
Jul 15, 2010

Learn about IC Validator flows and features, including advanced layout parameter extraction with StarRC, interactive LVS Shortfinder and Blackbox LVS to enable faster design convergence.
Kerstin McKay, CAE Director, Synopsys
Jun 09, 2010

With process geometries reaching 45-nanometers (nm) and below, there are many nanometer effects that can impact timing. Accurate analysis of these effects is required to identify potential timing issues. Synopsys’ NanoTime tool is the transistor-level static timing analysis (STA) solution that addresses the challenges in signal integrity (SI) analysis associated with custom designs. In addition, over traditional STA, Multi-Input Switching (MIS) will play a role in the speedup or slowdown of paths.
Chad Lawrence, Staff Engineer, CAE, Implementation Group, Synopsys; Brad Roetcisoender, Senior Staff R&D Engineer, Implementation Group, Synopsys
Apr 22, 2010

This technical webinar will explain how Galaxy Constraint Analyzer (GCA) helps improve designer productivity through look-ahead timing constraint analysis and debug technology tuned for the Synopsys Galaxy Implementation Platform. Attendees will learn how early feedback on constraint quality leads to more efficient runtimes and better quality of results in Synopsys’ Design Compiler® synthesis and IC Compiler physical implementation and PrimeTime timing signoff tools.
Savino Grillo, Manager, CAE, Synopsys Implementation Group, Synopsys; Lionel Corbet, Staff Engineer, CAE, Synopsys Implementation Group, Synopsys
Apr 07, 2010

This webinar covers the following: early incremental power network fix guidance within ICC based on PrimeRail’s rail checking capability, PrimeRail’s inrush analysis capability for switch architecture control design during the IC Compiler design planning phase, and finally an ECO placement link after routing using PrimeRail’s decoupling capacitance analysis and insertion.
Li-Pen Yuan, Group Director, R&D, Implementation Group
Mar 24, 2010

How Advanced On-Chip-Variation works in comparison to flat-derate OCV and SSTA-based signoff technologies. Techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism.
Uyen Tran, Director CAE, Synopsys; Norb Heindl, Senior Staff Engineer, CAE, Synopsys
Feb 17, 2010

A discussion on the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. Learn about PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff.
Tzong-Maw Tsai, Director, Corporate Applications Engineer, Synopsys; Troy Epperly, Corporate Applications Engineer, Synopsys
Jan 20, 2010

Learn how StarRC Custom enables high accuracy and optimized extraction for improved simulation throughput. Demonstrations include a 3-D field solver, context-specific MOS device parasitic extraction, CustomSim simulation efficiency links and OpenAccess-based integration with Custom Designer.
Baribrata Biswas, Group Director, R&D / Extraction , Synopsys; Omar Shah, CAE / Extraction, Synopsys
Nov 11, 2009

Join our experts to learn how you can use In-Design Rail Analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, helping you accelerate the path to final design closure.
Tom Chau, Group CAE Director, Synopsys; Dr. Henry Sheng, R&D Group Director, Synopsys
Jun 25, 2009