This technical webinar will explain how Galaxy Constraint Analyzer (GCA) helps improve designer productivity through look-ahead timing constraint analysis and debug technology tuned for the Synopsys Galaxy Implementation Platform. Attendees will learn how early feedback on constraint quality leads to more efficient runtimes and better quality of results in Synopsys’ Design Compiler® synthesis and IC Compiler physical implementation and PrimeTime timing signoff tools.
Savino Grillo, Manager, CAE, Synopsys Implementation Group; Lionel Corbet, Staff Engineer, CAE, Synopsys Implementation Group
Apr 07, 2010

This webinar covers the following: early incremental power network fix guidance within ICC based on PrimeRail’s rail checking capability, PrimeRail’s inrush analysis capability for switch architecture control design during the IC Compiler design planning phase, and finally an ECO placement link after routing using PrimeRail’s decoupling capacitance analysis and insertion.
Li-Pen Yuan, Group Director, R&D, Implementation Group, Synopsys, Inc.
Mar 24, 2010

This technical webinar will explain how Advanced On-Chip-Variation works in comparison to flat-derate OCV and statistical STA-based signoff technologies, and will contrast the cost of adoption and accuracy of these three methods. Attendees will learn techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism through customer examples of deployment at 65nm and 45nm technology nodes. This 30 minute webinar will be followed by a Q&A session with our Corporate Applications and R&D teams.
Uyen Tran, Director, CAE, Synopsys Implementation Group; Norb Heindl, Senior Staff Engineer, CAE, Synopsys Implementation Group
Feb 17, 2010

Join us for a technical seminar that will discuss the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. This webinar will provide PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff. This 30-minute webinar will be followed by a Q&A session with our Corporate Applications and R&D teams.
Tzong-Maw Tsai, Director, Corporate Applications Engineer, Implementation Group, Synopsys, Inc., Troy Epperly, Corporate Applications Engineer/Implementation Group, Synopsys, Inc.
Jan 20, 2010

The widespread use of custom circuits in today’s advanced system-on-chip designs is creating a severe design and simulation bottleneck. Increasing complexity combined with the modeling of new parasitic effects are exacerbating the accuracy concerns as well as resulting in 2-4x increase in simulation runtimes. In this webinar, our experts will explain how StarRC Custom’s unique solution enables high accuracy and optimized extraction for improved simulation throughput. Technologies that will be demonstrated include unified 3D field solver, context-specific MOS device parasitic extraction, CustomSim simulation efficiency links and OpenAccess based integration with the Galaxy Custom Designer implementation solution.
Baribrata Biswas, Group Director, R&D / Extraction , Synopsys Inc.; Omar Shah, CAE / Extraction, Synopsys Inc.
Nov 11, 2009

Star-RCXT™ provides unique gate-level extraction techniques to address productivity bottlenecks in physical implementation and signoff. Our experts demonstrate how the latest process modeling and extraction features can help you achieve accurate and faster signoff.
Krishnakumar Sundaresan, Principal Engineer at Synopsys; Hong Liu, CAE for extraction products at Synopsys
Jul 21, 2009

Join our experts to learn how you can use in-design rail analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, helping you accelerate the path to final design closure.
Tom Chau
Jun 25, 2009

Attend this webinar to learn how to use signoff-driven SI-closure to keep your schedule on track and your performance on target.
Dr. Henry Sheng; Dr. Jinan Lou
Apr 27, 2009

In this webinar our experts will explain innovative techniques, such as "context-specific" and "active-node" based extraction to boost simulation performance and capacity for your custom, digital, memory or AMS designs.
Omar Shah
Apr 22, 2009