StarRC Custom

Overview
StarRC™ Custom is the advanced parasitic extraction solution architected for next-generation custom digital and analog/mixedsignal (AMS) IC designs. A key component of the Synopsys Galaxy™ Implementation Platform, it is built on Synopsys’ proven gold standard extraction technologies but uniquely tooled for custom design in advanced process technologies. StarRC Custom expands Synopsys’ custom design portfolio consisting of leading products such as Galaxy Custom Designer™ mixed-signal implementation solution, IC Validator physical verification solution, and CustomSim™ and HSPICE circuit simulation solutions.

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StarRC Custom Solution
The convergence of computing, consumer, mobile and wireless multimedia applications necessitates integrating complex custom digital and analog functions in today’s advanced system-on-chip (SoC) designs. However, the widespread use of custom IP is creating increased design and analysis bottlenecks for the design teams. Increasing transistor counts, process variation and the emergence of new parasitic effects at advanced technologies are exacerbating the accuracy and performance concerns associated with high-sensitivity custom designs. IC designers need a comprehensive parasitic extraction solution to address the exceptional challenges of critical custom circuits in their designs.

StarRC Custom addresses the needs of the next-generation custom IC designers by offering a unique solution consisting of unified gold standard extraction technologies of Star-RCXT™ and Raphael NXT coupled with advanced parasitic modeling. The combination of the two technologies enables StarRC Custom to deliver high performance with tuned accuracy to meet the stringent demands of the custom designs. In addition, StarRC Custom’s comprehensive offering including the seamless integration with Galaxy Custom Designer and optimized links with CustomSim simulator, enable increased designer productivity in implementation and simulation analysis resulting in overall faster time-to-tapeout (see Figure 1).

Figure 1: StarRC Custom is a key component of Galaxy Implementation
Platform and Synopsys’ custom design portfolio

Benefits

Unified Gold Standard Extraction Technologies
For timing-sensitive circuits such as small critical nets, AMS/RF and highspeed digital functions, accuracy is a non-negotiable design criterion. Designers generally require higher accuracy for such critical IP and circuits compared to the rest of the design but without severely impacting the overall turnaround time. In the StarRC Custom product, Synopsys’ gold standard extraction technologies, consisting of high-performance ScanBand extraction and Raphael NXT 3D fast field solver extraction, have been unified into a single solution (see Figure 2). The trusted sub-femto Farad accuracy of ScanBand technology is the foundation of the StarRC Custom solution providing the signoff accuracy and performance. The 3D field solver extraction technology brings more flexibility to the solution, especially for circuits where higher accuracy 3D self and coupling capacitance extraction is needed. The combination of the two technologies allows StarRC Custom to easily tune the extraction for targeted accuracy and productivity, as needed by the designers.

Figure 2: The unified gold standard extraction technologies in StarRC Custom
deliver high accuracy and performance for custom IC designs

Advanced Parasitic Modeling
Increasing process variation and new parasitic effects introduced at each new generation of process technology are significantly increasing design challenges, particularly for highsensitivity custom designs. Advanced process technologies are elevating a variety of physical effects once considered secondary to primary factors affecting circuit behavior, thus increasing the need for accurate modeling to mitigate the chances of silicon failure and lower yields. StarRC Custom delivers a high-accuracy solution for advanced nodes by modeling complex physical effects in smaller geometries and by accounting for every capacitive interaction in custom circuits.

At smaller process geometries, device parasitics have an increased impact on circuit behavior, especially in the case of transistor-level custom circuits. For example, gate-to-contact capacitance can have an amplified impact on device performance due to the Miller effect. Device parasitics are becoming “context-specific” at advanced nodes, that is, they are becoming more sensitive to the layout environment requiring higher levels of accuracy in extraction. StarRC Custom accurately models and extracts the device-level effects such as contact etch effect, gate-to-contact and gate-to-diffusion fringe capacitances for increased signoff accuracy (see Figure 3a, 3b).

Figure 3: StarRC Custom’s advanced parasitic modeling provides signoff accuracy

CustomSim Circuit Simulator Integration
Post-layout simulation runtimes are increasing 2-4x with every new process generation. More accurate and efficient parasitic extraction is needed to accelerate simulation and meet tapeout schedules. StarRC Custom offers seamless integration with Synopsys’ industry-leading CustomSim circuit simulator and a wide range of innovative features to boost simulation performance and capacity while preserving signoff accuracy. StarRC Custom’s exclusive interface with CustomSim includes selective device parasitic extraction, active node (critical net) extraction, post-layout acceleration with isomorphic hierarchical backannotation and optimized power network extraction (TARGET_PWRA) for faster in-design rail analysis (see Figure 4). The integration between the two tools enables over 10x simulation performance speedup for custom IC and memory designs.

Figure 4: StarRC Custom’s highly optimized links with CustomSim offer increased simulation performance

Custom AMS Design Platform Integration
StarRC Custom is integrated with Synopsys’ Galaxy Custom Designer mixed-signal implementation system and with Cadence’s Virtuoso Analog Design Environment (ADE) for custom AMS and custom digital designs. StarRC Custom and Galaxy Custom Designer offer users the unique benefits of an OpenAccess interface combined with the ease-of-use of the familiar Synopsys implementation environment using a common data flow. StarRC Custom provides full probing capabilities to probe parasitics within the parasitic view or within the matching schematic view (see Figure 5). The parasitic prober allows users to interactively observe point-to-point resistance, total net capacitance, net-to-net coupling capacitance and cross-probing between schematic and parasitic views. It also provides the ability to output probed parasitics to an ASCII report file, and to annotate parasitic view total capacitance values to an associated schematic view.

Figure 5: StarRC Custom integration with Galaxy Custom Designer enables productive cross-probing and simulation debugging

Other Key Features

Process Modeling

Productivity and Ease-of-use

Specifications

File Format Support StarRC Custom supports the following industry-standard formats and interfaces:

System Requirements

Platform/OS