Design Compiler® in the Galaxy™ Implementation Platform maximizes your productivity with its suite of RTL synthesis and test solutions. The premier synthesis product, DC Ultra, lets you accurately predict post-layout timing, area and power during RTL synthesis, to significantly reduce costly and time-consuming design iterations. The latest addition to the product family is Design Compiler Graphical, a tool that helps RTL designers predict, visualize and alleviate wire routing congestion early in the design flow, prior to physical implementation. The Design Compiler family also includes the award-winning Galaxy Test solution, offering designers the fastest and most cost-effective path to high-quality manufacturing tests and working silicon; Power Compiler™, a complete solution for power synthesis and optimization; the Formality® equivalence checker; and the DesignWare® library with its unequalled variety of synthesizable IP. These best-in-class, production-proven solutions are integrated to achieve the industry’s fastest and most predictable RTL-to-GDSII flow.