Scan design, the ubiquitous design-for-test technology, is based on a relatively simple concept: One or more scan chains are constructed on a chip by serially tying together a set of internal registers and flip-flops.
Rohit Kapur & Robert Ruiz, Synopsys

Design Compiler 2009.06 boosts designer’s productivity with many new advanced features. The 2009.06 release includes faster runtimes on multicore machines and concurrent optimizations across all scenarios such as leakage and timing, enabling designers to achieve better QoR.
Liz Chambers & Mary Ann White, Implementation Group Synopsys

Running automatic test pattern generation (ATPG) on a single processor may take a week or longer to complete, especially for very large designs and when testing at-speed fault models. Designers and test engineers need a straightforward way to reduce ATPG runtime by many factors and deliver working test patterns in days, not weeks.
Cy Hay, Product Manager

Formality is an equivalence-checking solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. Formality delivers superior completion on designs compiled with DC Ultra.
Erin Hatch Formality CAE, Synopsys

Exponential growth in size and complexity of systems on a chip (SoCs), coupled with increasingly stringent quality mandates, demand an efficient and productive approach for register-transfer-level (RTL) designers implementing design-for-testability (DFT).
Robert Ruiz Test Product Marketing Manager, Synopsys, Inc.

A predictable RTL to GDS11 design flow is esential for the completing designs on time. Synopsys' DC Ultra(TM) topographical technology accurately prdeicts layout results, such as timing, area, and power during synthesis, and delvers a predictalbe RTL-to GDS11 implementation flow.
Synopsys

As the design community moves to the complete adoption of physical synthesis solutions, it is becoming evident that testability must be taken into account at all stages of the design process.
Synopsys, Inc.

SystemVerilog is an IEEE approved (IEEE P1800-2005) Hardware Description Language. It provides superior capabilities for system architecture, design, and verification.
Synopsys