Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities

Synopsys announced that Oticon taped out the digital signal processor (DSP) chipset for their next-generation hearing-aid devices ahead of schedule using Synopsys' Design Compiler™ Graphical RTL Synthesis, a key component of the Galaxy™ Implementation Platform.

Synopsys announced that Samsung Electronics' Foundry business (Samsung Foundry) has successfully taped out its first 32-nanometer (nm) system-on-chip (SoC) design using Synopsys' Galaxy™ Implementation Platform.

Delivers Five Percent Correlation to Layout, Floorplan Exploration and 2X Faster Runtime with Multicore Technology

Eliminates Iterations Between Synthesis and Place and Route to Predictably Meet Performance and Time-to-Market Goals

Multicore Processing Speeds Runtime by 3X, Accelerates Time-to-Quality

Delivers predictable high compression with only one pair of test data pins

Design-centric yield management enables product engineers to achieve rapid yield ramp and provide cost-effective yield control in volume production

IEEE 1801 Enabled Implementation Flow Qualified for 65- and 40-nm Designs

Unique Power-Aware Test Capabilities Reduce Yield Loss

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today unveiled its new Design Compiler® Graphical synthesis product that shortens implementation time for system-on-chip (SoC) devices by helping RTL designers avoid wire-routing congestion problems that typically occur during detailed route.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that STMicroelectronics has adopted Synopsys' TetraMAX® small delay defect (SDD) automatic test pattern generation (ATPG) and failure diagnostics solution to provide higher-quality manufacturing tests for its system-on-chip (SoC) products.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that CASIO COMPUTER CO., Ltd. has adopted Synopsys' Design Compiler® topographical technology to shorten the design schedule for its next-generation EXILIM® digital camera chips.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that IBM has added support for topographical technology in its 90-nanometer (nm) and 65nm-based application-specific integrated circuit (ASIC) design kits.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced availability of the latest release of its Design Compiler® synthesis solution, Design Compiler 2007.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that it has enabled STMicroelectronics to achieve first-silicon success for its new STi7200 dual-video-stream high-definition (HD) decoder, aiming to serve a broad range of digital consumer applications including set-top boxes, high-definition DVDs (dual-standard Blu-ray and HD-DVD) and digital TVs.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that that STMicroelectronics (NYSE: STM), a leading supplier of semiconductors, has deployed Synopsys Design Compiler® topographical technology in its 90-nanometer (nm) and 65-nm application-specific integrated circuit (ASIC) design flow to expedite design time.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that the Semiconductor Technology Academic Research Center (STARC) has deployed Synopsys Design Compiler® topographical technology in its 65-nanometer (nm) Synopsys Galaxy™ Design Platform-based design flow (project name: Eagle Flow) in the STARCAD®-CEL methodology.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that the Electronics and Telecommunications Research Institute (ETRI), Korea's leading research and development organization, has used Synopsys Design Compiler® topographical technology to expedite the tapeout of their new 90-nanometer (nm) multimedia chip.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that Displaytech Inc., a world leader in ferroelectric liquid-crystal-on-silicon (FLCOS) microdisplays, has moved to the Synopsys Design Compiler® synthesis tool in designing its next-generation FLCOS backplane for high-resolution, high-speed microprojection and holographic data storage (HDS) systems.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that Progate Group Corporation (PGC), one of the largest SoC/ASIC design service providers in Taiwan, has adopted Synopsys' Design Compiler® topographical technology to help accelerate time-to-market for its products.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that its DFT MAX scan compression automation solution has been instrumental in reducing test costs related to data inflation on more than 50 successful tapeouts since its general release in September 2005. CSR, Genesis, Micronas, NVIDIA Corporation, and more than 50 other leading semiconductor firms are using this tool to reduce test costs on their nanometer designs.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that ARM, DSP Group Inc., Freescale, Infineon Technologies AG, Matsushita Electric Industrial Co., Ltd., Realtek Semiconductor Corp., Samsung, STMicroelectronics, Toshiba, UMC and others have successfully taped out more than 15 multi-voltage designs with Synopsys' Galaxy™ design platform RTL-to-GDSII advanced low-power solution.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced the availability of the ARM-Synopsys Galaxy™ Reference Methodology (RM) with support for Synopsys' Design Compiler® topographical technology.