Design Compiler Graphical

Overview
Design Compiler® Graphical is designed to increase designer productivity for both synthesis and place and route through creation of a better starting point for physical implementation and eliminating costly iterations between synthesis and place and route. It extends DC Ultra™ topographical technology to predict circuit congestion “hot spots” early in the design flow, provides designers with visualization of congested circuit regions and performs specialized synthesis optimizations to minimize congestion in these areas. This enables RTL designers to avoid wire-routing congestion problems that occur during detailed routing. Additionally, it provides RTL designers access to IC Compiler’s design planning capabilities from within the synthesis environment. With the push of a button, they can perform what-if floorplan exploration to identify and fix floorplan issues such as timing issues due to macro locations and achieve an optimal floorplan efficiently.

Design Compiler Graphical applies additional physical optimization techniques and considers the effects of smaller geometries such as coupling capacitances for accurate delay modeling. It produces physical guidance to IC Compiler placeand- route solution tightening timing and area correlation to 5% while speeding-up IC Compiler placement by 1.5X. The physical guidance passed to IC Compiler streamlines the flow for a faster, predictable and convergent path from RTL to GDSII. In addition, Design Compiler Graphical includes a scalable multicore infrastructure designed to deliver significant runtime speed-up on multicore compute servers yielding 2X faster runtime on four cores.

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Key benefits

Figure 1: Congestion map

Figure 2: Design Compiler Graphical results

Traditional Approach to Fixing Routing Congestion
With increasing design functionality coupled with shrinking device sizes, routing congestion issues can result in designs that are difficult to route and lead to substantial schedule delays. Routing congestion occurs when the resources (tracks) needed to route the design exceed the available resources. In other words certain areas of a design are congested when the number of physical wires needed to connect the gates that make up the logic exceeds the space available to route the wires.

Without Design Compiler Graphical, a design’s wire-routing congestion ‘footprint’ is not available to the designer until well into place and route. This footprint is called a congestion map and the color distribution of the map indicates the relative routability of the design. Large concentrations of white and red indicate areas of high congestion, with blue representing the least-congested areas. Figure 1 shows a congestion map generated after layout. As indicated by the amount of red in the congestion map, a significant portion of the design is congested. There is a very high likelihood that this design will have trouble routing.

During place and route designers deploy various techniques to alleviate congestion. These techniques can include changes to the floorplan such as port or macro locations, changing target gate utilization, adding placement blockages, etc. Making such changes during place and route is time consuming and can lead to schedule delays. Furthermore, these techniques may not work and the designer may be required to iterate back to the RTL and recode the RTL source to remove congestion-causing design characteristics. These options are not optimal and can lead to missed schedules, missed design goals and result in added costs.

Design Compiler Graphical Provides Accurate Congestion Prediction in Synthesis
Design Compiler Graphical includes Synopsys’ virtual global-routing technology that enables designers to predict wire-routing congestion during RTL synthesis. This technology allows designers to identify and fix design issues to reduce routing congestion, eliminating costly iterations between synthesis and physical implementation to achieve their design goals and speed up place and route.

Figure 2A shows a congestion map as predicted by Design Compiler Graphical and Figure 2B shows the congestion map in IC Compiler after optimizing the design in place and route to reduce congestion. It is clear that Design Compiler Graphical is able to identify the design’s highly congested areas during RTL synthesis, thus providing designers with valuable information on the design’s ability to route during place and route.

Early Physical Visualization
Design Compiler Graphical includes a physical viewer that allows RTL designers to view layout congestion in their design during synthesis, as shown in Figure 3. Routing congestion that is related to floorplan, such as macro placement or port location, cannot be automatically optimized in synthesis. These congestion issues can only be resolved by changing the floorplan. Using Design Compiler Graphical’s physical viewer, designers can identify floorplan issues such as sub-optimal macro or port locations that are causing timing violations or congestion “hot-spots” and use the push-button floorplanning capability described later to take corrective measures to alleviate congestion problems before place and route.

These interactive visualization capabilities also include the ability to cross-highlight suspect physical cells in the congestion map to the netlist, as shown in Figure 4. This allows the designer to easily isolate problem timing paths and make necessary changes during RTL synthesis.

Figure 3: Interactive analysis of congestion map in Design Compiler Graphical

Figure 4: Design Compiler Graphical physical view

Congestion-Driven Optimization in Synthesis
Once it is identified that the design is congested and the congestion is not related to the floorplan, the next step is to fix the congestion in synthesis. Design Compiler Graphical provides an automated way to optimize the RTL to reduce routing congestion. It performs specialized optimizations to generate a routing-friendly netlist topology that minimizes highly-congested structures and wire crossings in congested areas. By intelligently choosing netlist structures that are easier to route, Design Compiler Graphical can generate a netlist that is a better starting point for physical implementation, leading to faster place and route.

Figure 5A shows the congestion characteristics of the same design highlighted in Figure 2A. Figure 5B shows this design after optimizing it to reduce congestion using Design Compiler Graphical. It clearly shows that the congestion optimization technology has significantly reduced wire-routing congestion in synthesis, resulting in a design with minimal to no congestion as shown in Figure 5C after placement in IC Compiler. Design Compiler Graphical has automatically optimized this design to minimize wire-routing congestion by taking into consideration the congestion characteristics of the synthesized cells. Design Compiler Graphical congestion optimization also automatically reduces congestion of high levels of adaptive scan compression.

Figure 5: Design Compiler Graphical and IC Compiler congestion maps

Push-Button Floorplan Exploration
Topographical technology in Design Compiler Graphical empowers RTL designers to detect and fix design issues early during synthesis and prevent unwanted surprises late in the design flow. With the physical viewer RTL designers can see the impact of floorplan on routing congestion or timing violation. However, if changes to floorplan were needed to fix timing or congestion issues, RTL designers had to ask their counterparts on physical design teams to adjust the floorplan, resulting in iterations between the teams and schedule delays. Design Compiler Graphical provides RTL designers access to IC Compiler design planning capabilities from within the familiar synthesis environment. After detecting design issues, such as routing congestion or timing violations due to floorplan characteristics, RTL designers can now amend the floorplan and re-synthesize the design with an updated floorplan without ever leaving the synthesis environment. The IC Compiler design planning menus have been simplified to give RTL designers ease of use for simple floorplan modifications. An option is available for expert users to utilize the full, floorplanning capabilities. The link between Design Compiler Graphical and IC Compiler design planning is transparent to users hence no set-up or data transfer is required. Once a designer has created an optimal floorplan, he/she can save the floorplan to be used for physical implementation downstream.

Physical Guidance to IC Compiler
With designs becoming more complex along with shrinking geometries, designers require even tighter correlation between synthesis and layout results. Additionally, as geometries become smaller, the coupling capacitance between adjacent parallel wires is much higher due to the fact that spacing between wires is smaller and the relative heights of the wires are greater. Hence the impact of coupling capacitance is much higher on wire delays and needs to be accounted for in synthesis.

Topographical technology in Design Compiler Graphical has been extended to perform additional physical optimizations during synthesis, to accurately model the effects of smaller geometries such as coupling capacitance and to create a better starting for physical implementation. It creates physical guidance for IC Compiler to seed its placement bringing synthesis timing and area results within 5% of layout results while speeding up the IC Compiler placement step by 1.5X. This tight correlation between synthesis and layout enables designers to identify and fix timing and area issues in their design during synthesis to avoid lengthy iterations with place and route and get better results much faster.

Multicore Infrastructure Delivering 2X Faster Runtime on 4 Cores
The advent of multicore processors in computer platforms has boosted the processing power available to designers. Design Compiler Graphical has a scalable infrastructure to take advantage of multicore compute servers. Using an optimized scheme of distributed and multithreaded parallelization, Design Compiler Graphical delivers a 2X improvement in runtime on quad-core platforms. The new infrastructure delivers runtime benefits without varying the quality of results.

Multi-Mode, Multi-Corner (MCMM) Synthesis
Today’s complex designs run under multiple conditions and in many modes, such as scan, sleep and other functional modes. Optimizing serially across each mode and several operating conditions can be time-consuming and require multiple iterations to achieve optimal results. With Design Compiler Graphical, RTL designers can analyze and optimize designs across multiple modes and corners concurrently to substantially drive down design development time and cost.

Easy to Adopt
Design Compiler Graphical is designed for seamless integration into the current RTL synthesis use model. It uses the same setup as DC Ultra topographical technology. Similarly, it is designed for RTL designers, does not require deep physical design expertise, and improves productivity by enabling more informed decisions during RTL synthesis with early visibility into what the design characteristics will be during place and route. The inputs to Design Compiler Graphical, which are the same as DC Ultra with topographical technology, are listed below and also shown in Figure 6:

Design RTL
Logical Library (db)
Physical Library (Milkyway™)
Design constraints (SDC)
Optional physical constraints (Floorplan)

The output is a netlist optimized for timing, area, test, power and congestion with accurately-predicted layout results, ready for physical implementation hand-off. In addition, physical guidance for Synopsys place-and-route solution IC Compiler can be created, tightening timing and area correlation to 5 percent while speeding up IC Compiler’s placement phase by 1.5X.

Figure 6: Design Compiler Graphical inputs and outputs

Conclusion
Design Compiler Graphical significantly boosts RTL designers’ productivity. It provides the ability to accurately predict, visualize and alleviate routing congestion, creating an easy-toroute netlist substantially reducing iterations between synthesis and physical implementation. It enables RTL designers to perform floorplan exploration from within the synthesis environment and converge on the optimal floorplan faster. In addition, it accurately models the effects of smaller geometries, deploys advanced physical optimizations and generates physical guidance for IC Compiler place-androute solution to further tighten the correlation and accelerate physical implementation. Design Compiler Graphical is 2X faster on multicore compute servers while ensuring zero deviation of synthesis results. It also optimizes designs across multiple modes and corners concurrently to achieve optimal results faster.

Availability
Design Compiler Graphical is available now as an add-on to DC Ultra.