DFTMAX

Overview
DFTMAX compression is a comprehensive scan compression solution that addresses the cost challenges of testing designs fabricated in 130-nm and smaller process technologies. These deepsubmicron (DSM) designs can have subtle manufacturing defects that are only detected by applying DSM tests, such as at-speed and bridging tests, in addition to stuck-at tests. The extra patterns needed to achieve high test quality for these designs increase both the test time and the volume of test data, resulting in higher test costs.

DFTMAX compression reduces these costs by delivering push-button 10-100x test data and test time compression with very low silicon area overhead. Seamlessly enabling compression in TetraMAX® ATPG, and encapsulated in Synopsys’ Galaxy™ Design Platform, DFTMAX compression achieves predictable results with virtually zero impact on timing.

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Key Benefits

DFTMAX Features

Figure 1: DFTMAX compression delivers 10-100X test time and test volume reduction

Figure 2: DFTMAX Compression

DFTMAX Compression Delivers 10-100x Test Time and Test Volume Reduction
DFTMAX compression reduces the costs of nanometer testing by providing 10-100x test data volume compression (Figure 1) within design synthesis. Using Synopsys’ patented “Adaptive Scan” compression architecture, DFTMAX compression saves test time and makes it possible to include DSM test patterns in tester configurations where memory is limited. With the industry’s most area-efficient solution, DFTMAX compression has virtually no impact on design timing and results in the same high test coverage as using TetraMAX ATPG with standard scan (Figure 2).

Test Compression Synthesis
DFTMAX compression synthesis flow is similar to the existing DFT Compiler flow. It synthesizes scan and test compression directly from RTL to testable gates with full optimization of synthesis design rules and constraints. All test and compression requirements specified prior to the synthesis process are met concurrently with area, timing and power optimization. DFTMAX compression creates a gate-level implementation with all scan design rules checked and all test and compression logic verified, leading to very high and predictable test coverage and test compression results. The implementation of DFT, including test compression, within the design synthesis environment allows problems to be found and fixed earlier in the design cycle, thus avoiding ‘schedule-breaking’ design iterations. DFTMAX compression also enables TetraMAX ATPG to seamlessly generate compressed test patterns having the highest test quality.

Figure 3: Test compression synthesis flow

Integration With Galaxy Design Platform For Concurrent Optimization Of Area, Power, Timing, Physical And Test Constraints
In Synopsys’ unique synthesis flow (Figure 3), Adaptive Scan compression logic is synthesized simultaneously with scan chain stitching within the Galaxy Design Platform. Topographical scan chain ordering and partitioning provides excellent timing and area correlation with physical results using IC Compiler. This enables designers to achieve area, power, timing and DFT closure simultaneously. DFTMAX compression writes detailed scan chain information to the Synopsys design database which IC Compiler then reads to perform further optimizations to reduce area impact and decrease overall routing congestion (Figure 4).

Integrating DFT resources into a complex multi-voltage design can be a time-consuming and error-prone process without automation tailored for low-power flows. Once voltage domain characteristics of the design with UPF (unified power format) are specified, DFTMAX compression automatically inserts level shifters and isolation cells during scan chain implementation. To reduce routing congestion and area impact of the DFT logic, DFTMAX compression minimizes both scan chain crossings between power/voltage domains and the number of level shifters inserted.

Figure 4: These screen captures show DFTMAX compression results without the routing congestion associated with standard scan

Complete DFT Rules Checking
DFTMAX compression enables designers to create “test-friendly” RTL. It identifies DFT rules violations early in the design cycle during the pre-synthesis stage to avoid design iterations. The DFT rules checker validates that the design is compliant with scan rules leading to ensure operational scan chains and the highest test coverage. The violations can be debugged using a graphical browser in Design Vision. It has comprehensive rules checks for:

Violations that prevent proper scan operation
Violations that prevent data capture
Violations that lower fault coverage

The same TetraMAX ATPG DRC engine is run from RTL to gate level, making it possible for designers to validate testability all the way through the design synthesis process.

Hierarchical Scan Synthesis
To handle test synthesis of very large designs, some level of abstraction is required so that the system/chip integrator can reduce design time. By abstracting the DFT information in a test model, along with timing and placement information, DFTMAX compression enables quick hierarchical test implementation of multi-million gate designs.

Boundary Scan Synthesis And Compliance Checking To The 1149.1/6 Standard
DFTMAX compression delivers a complete set of boundary scan capabilities including:

TAP and BSR synthesis
Compliance checking to the IEEE 1149.1/6 standard
Boundary Scan Description Language (BSDL) file generation
Functional and DC parametric pattern generation for manufacturing test

Figure 5: DFTMAX compression fully supports proven TetraMAX ATPG ATE links for an effective and accurate yield diagnostics solution

Transparent Integration In TetraMAX ATPG For Power-Aware Test
DFTMAX compression transfers all information about the Adaptive Scan compression architecture to TetraMAX ATPG to automatically generate compressed, power-aware test patterns with highest test coverage. DFTMAX compression supports all existing TetraMAX ATPG engines and DSMTest fault models.

Integration With TetraMAX ATPG Diagnostics
DFTMAX compression fully supports proven TetraMAX ATPG ATE links for failure diagnosis and delivers a straightforward flow from tester fail to location of the defect. DFTMAX compression and TetraMAX ATPG diagnostics together deliver a very effective and accurate yield diagnostics solution (Figure 5).