Widely deployed by semiconductor companies across all industry segments, DFTMAX™ compression now delivers even greater test cost savings by enabling up to 100X or more test data volume/test application time reduction with as few as one pair of test data pins. Extending Synopsys’ patented adaptive scan technology with high performance, low-pin interface to the tester addresses higher scan compression requirements stemming from increased adoption of a variety of hierarchical design techniques and cost-effective test methodologies that mandate few test pins. DFTMAX compression for pin-limited test facilitates cost-effective chip testing and diagnostics, achieving the same high quality-of-results and ease-of-use Synopsys’ test customers have come to expect.
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