Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill |
Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays. This paper presents a pushbutton flow to generate timing-aware, signoff quality metal fill during place and route. David Pemberton-Smith |
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Enhancing the DRC Waiver Methodology for Layout Verification Productivity |
To manage design violations, CAD departments have employed a number of solutions to reduce the amount of violations needed to be checked by the physical verification engineer. However, these solutions are limited. Jason Puryear |
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Accelerating Physical Verification with an In-Design Flow |
There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process. Elango Velayutham |
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Following the Rules is Not Quite Sufficient |
Smaller technologies, shorter time to market windows and more complex designs are driving the need for an
additional set of analysis techniques which will help designers understand how susceptible their designs are
to manufacturing process variations Technology nodes larger than 90 nm were able to achieve a certain level
of manufacturability by complying with a set of foundry design rules. Kuo H. Wu, PhD and Marilyn Adan |
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Achieving Optimal Performance Scalability for Physical Verification |
Physical verification runtimes and memory usage have exploded with the increasing number of design
rules, their subsequent complexity and the size of chips to be verified. Rahul Kapoor, Marilyn Adan, and Louis Schaffer
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