INTERNATIONAL
|
SOLVNET
Home
Tools
Implementation & SignOff
Physical Verification
Webinars
Webinars
IC Validator Webinar
In-Design physical verification for faster Time-to-Tapeout
Synopsys
May 11, 2009
IC Compiler Videolog
IC Compiler Ecosystem: Value Links in Galaxy Implementation Platform Speed Design Closure
NEW! IC VALIDATOR
In-Design Physical Verification
IC Validator Webinar
In-Design physical verification for faster time to tapeout
IC COMPILER ZROUTE
State-of-the-art routing technology fully integrated into IC Compiler
WHITE PAPERS
IC Design to Signoff Verification
News
TSMC and Synopsys Collaborate on Interoperable Unified Physical Verification Formats
Achronix Deploys Synopsys IC Validator and IC Compiler for Next-Generation FPGA....
Aquantia Deploys Synopsys IC Validator and IC Compiler for 40nm Quad 10GBASE-T Design
Synopsys Launches IC Validator, Offers Significant Reduction in Physical....
Synopsys IC Validator Adopted by NVIDIA for Sign-Off Physical Verification
Silicon Canvas Laker Environment Integrates With Hercules Physical Verification....
Synopsys Enables STMicroelectronics to Achieve First-Silicon Success for
More
All Synopsys News
Articles
A scalable approach to speeding physical verification
More
White Papers
Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill
Enhancing the DRC Waiver Methodology for Layout Verification Productivity
Accelerating Physical Verification with an In-Design Flow
Following the Rules is Not Quite Sufficient
Achieving Optimal Performance Scalability for Physical Verification
More
Webinars
IC Validator Webinar
More
Videos
DAC 2009: IC Compiler Ecosystem
IC Validator for In-Design Physical Verification
More
IC COMPILER
STARRC
Custom Designer
GALAXY PLATFORM
Lynx Design System
Solvnet
IC Validator
© 2010 Synopsys, Inc. All Rights Reserved.
Contact us
|
Locations
|
Privacy
|
Legal
|
RSS