 |
Fastest Time to Tapeout with IC Validator
Learn about IC Validator flows and features, including advanced layout parameter extraction with StarRC, interactive LVS Shortfinder and Blackbox LVS to enable faster design convergence.
Kerstin McKay, CAE Director, Synopsys
Jun 09, 2010 | | | Eliminating Late-Stage DRC Surprises with In-Design Physical Verification
Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.
Kerstin McKay, CAE Director, Physical Verification, Synopsys
May 05, 2010 | | | PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure
This webinar covers the following: early incremental power network fix guidance within ICC based on PrimeRail’s rail checking capability, PrimeRail’s inrush analysis capability for switch architecture control design during the IC Compiler design planning phase, and finally an ECO placement link after routing using PrimeRail’s decoupling capacitance analysis and insertion.
Li-Pen Yuan, Group Director, R&D, Implementation Group
Mar 24, 2010 | | | In-Design for Faster Design Closure
First in a series addressing 32/28nm sign-off bottleneck challenges and the solutions best suited to mitigate these challenges. Learn how Synopsys’ In-Design solutions make it possible for place-and-route engineers to accelerate design closure by enabling signoff analysis from within the implementation flow.
Dan Page, Vice President of R&D, Implementation Group, Synopsys
Mar 02, 2010 | | | In-Design PV for Faster Time-to-Tapeout
Synopsys’ physical design and verification technologists will show you how in-design physical verification combines timing awareness and signoff accuracy to speed up your tapeout schedule.
Kerstin McKay, CAE Director, Physical Verification products, Synopsys
May 20, 2009 | | |
|
|