IC Validator is a complete physical verification tool, performing the increasingly complex DRC and LVS sign-off checks. In addition, it has been specifically architected for In-Design verification. In-design physical verification means that the Place and Route engineers can run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment.

The three cornerstones of IC Validator are

• High performance to run compute-intensive checks and DFM utilities, such as metal fills
• Foundry qualification for final signoff for DRC and LVS
• Seamless integration with Synopsys’ leading Place and Route solution, IC Compiler

Antun Domic Introduces IC Validator IC Validator is a full, sign-off quality verification tool that delivers the highest performance to enable significantly improved time-to-tapeout with better DFM closure. Hear what Antun Domic, senior vice president and general manager of Synopsys' Implementation Group, has to say about this new physical verification solution. Antun Domic, senior vice president and general manager of Synopsys' Implementation Group Click to play

Recent Press Releases

• TSMC and Synopsys Collaborate on Interoperable Unified Physical Verification Formats
• Aquantia Deploys Synopsys IC Validator and IC Compiler for 40nm Quad 10GBASE-T Design
• Achronix Deploys Synopsys IC Validator and IC Compiler for Next-Generation FPGA Design
• Synopsys Launches IC Validator, Offers Significant Reduction in Physical Verification Turnaround Time for Advanced Designs
• Synopsys IC Validator Adopted by NVIDIA for Sign-Off Physical Verification

Product Information

• IC Validator Datasheet

Webinar

• In-Design physical verification for faster time to tapeout

White Papers

• Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill
• Enhancing the DRC Waiver Methodology for Layout Verification Productivity
• Accelerating Physical Verification with an In-Design Flow