Resolving correlation issues is a time consuming step and is all the more challenging when it has to be done across multiple corners and modes. Tight correlation to signoff is critical for faster time to results. d d
Ashwini Mulgaonkar, Synopsys Implementation Group

Currently, most EDA tools do not provide a solution that addresses the limitations of a custom datapath flow. This paper discusses datapath designs, benefits, limitations, and the use of an automated datapath design capability that allows both custom and ASIC designers to meet aggressive design objectives with ever-tighter project deadlines.
Jafar Safdar, Synopsys Implementation Group

There are numerous techniques to achieve a low-power design and several approaches to structuring the flow. As a starting point, high performance designs require a benchmark proven low-skew, low-insertion delay CTS solution. Correlation to industry standard sign-off engines for accuracy and minimum data format translations are required to achieve fast design closure. The optimal solution includes complete low power capability throughout the design flow. This paper addresses low power design issues and includes technologies and techniques to achieve high performance, low power design goals.
Harvey Toyama, Synopsys Implementation Group

Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology, and the primary care-abouts for designers and CAD engineers. Increasingly manufacturability and yield have also become critical design objectives, and multiple design-for-manufacturability (DFM) optimization techniques have been added to the design flows. As manufacturability has been a secondary goal, conventional routers have been optimizing for it after timing optimization – the point at which all of the primary design goals have already been met. While this methodology has worked well up to the 65nm technology node, it starts to break down at 45nm and below. This paper talks about the routing challenges at 45nm and below and the need for modern DFM-friendly routing technologies for achieving better manufacturability and higher yield without sacrificing performance.
Maria Gkatziani, Synopsys Implementation Group

There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process. This paper provides a production-proven example of this flow.
Elango Velayutham

Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays. This paper presents a pushbutton flow to generate timing-aware, signoff quality metal fill during place and route.
David Pemberton-Smith

By its very nature, even the best conventional clock tree synthesis leaves both performance and variation tolerance potential on the table. Clock mesh offers the designer a means of achieving extreme high performance along with the avoidance of process variation effects. Long known as the clock distribution method for high-end microprocessors, clock mesh also offers significant variation tolerance. Clock mesh use to be an entirely manual, difficult to analyze technology, but new advances in clock mesh automation and analysis now enable it to be considered as a mainstream clock distribution solution.
Harvey Toyama, Synopsys Implementation Group

Today’s system on a chip (SoC) designs continue to get larger and more complex. Given that consumer products are now the main driver for SoC designs, design teams must deliver chips quickly to capture as much revenue as possible from the latest consumer trend. Flat implementation flows are inefficient in terms of computer system resource requirements and runtimes for large SoC designs. Teams are turning to hierarchical design flows to implement these designs. This paper discusses design exploration and planning in a hierarchical flow for large SoCs and delves into efficient techniques that produce fast turn times and a concurrent physical implementation that enables predictable design convergence.
Steve Kister, Synopsys Implementation Group