| Accellera Rolls Power Plan |
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Oct 15, 2008 |
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| Manufacturing Concerns Move Up the Design Cycle |
The expression "design-for-manufacturing" (DFM) has been bandied about for so long, that designers regard it with suspicion. They've been told many times that shrinking process nodes will force them into a realm that was once happily reserved for the engineers at the fab who turn designs into working silicon.
Sep 02, 2008 |
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| Synopsys revamps IC Compiler with multi-threaded routing technology |
Developed from scratch by a team assembled specifically for their routing design experience, Mountain View, Calif.-based semiconductor design and manufacturing software supplier Synopsys Inc today rolled out Zroute, a new multi-threaded router that is completed integrated into the company’s IC Compiler physical design software.
May 27, 2008 |
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| Synopsys unveils new IC Compiler router |
Synopsys, Inc. today unveiled Zroute, a new multi-threaded router fully integrated into IC Compiler.
May 27, 2008 |
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| SCDsource: Synopsys rolls next generation IC router |
Synopsys already has a router in its IC Compiler product, but the company decided that customers needed something different for 45 nm and below. Synopsys this week (May 27) is rolling out ZRoute, a multi-threaded router that performs concurrent design for manufacturability (DFM) optimizations.
May 27, 2008 |
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| Semiconductor Int'l: Synopsys Unveils Faster Router |
Responding to the need to take better advantage of the multicore microprocessor architectures and solve 45 nm design for manufacturability (DFM) challenges in IC design, Synopsys Inc. (Mountain View, Calif.) introduced the Zroute compiler router.
May 27, 2008 |
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| EDA DesignLine: Design Challenges Drive Need for New Routing Architecture |
Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology. Increasingly manufacturability and yield have also become critical design objectives, especially for technology nodes at 90 nanometers (nm) and below.
May 27, 2008 |
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| Early relief for 45-nm routing congestion |
Moore's Law is both a blessing and a curse. Each new manufacturing process generation provides designers an opportunity to squeeze roughly twice the circuit functionality into an unchanged die area, significantly lowering fabrication costs for systems-on-chip (SoCs).
Apr 07, 2008 |
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| Synopsys donates technology to Accellera low-power effort |
SAN FRANCISCO — Top-tier EDA vendor Synopsys Inc. said Tuesday (Sept. 19) it has donated power management technology to the Unified Power Format (UPF) standardization effort of EDA standards organization Accellera.
Sep 19, 2006 |
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| Power integrity analysis for billion-transistor full-custom designs |
While the move to advanced process technologies has enabled levels of integration to reach new heights, engineers must now work harder than ever to realize those benefits.
Sep 17, 2006 |
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| How Much Test Compression is Enough? |
Each new manufacturing process generation brings with it a whole new set of challenges. In an era of multimillion-gate complexity and increasing density of nanometer manufacturing defects, a key challenge today is creating the highest quality deep submicron (DSM) manufacturing tests in the most cost-effective manner possible.
Feb 20, 2006 |
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| Critical Area Optimizations Improve IC Yields |
The move to advanced nanometer nodes and new process materials is diminishing semiconductor designers’ ability to estimate and realize device yields.
Jan 09, 2006 |
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