Synopsys, Inc. today announced that Ubixum has used Synopsys' Galaxy Custom Designer™ implementation solution to successfully design its latest advanced image sensor chip.

Speeds RTL-to-GDSII Turnaround Time Through Look-ahead Constraint Analysis

Synopsys, Inc. today introduced its In-Design Rail Analysis™ capability to accelerate design closure. Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.

Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that TSMC selected Synopsys' Galaxy™ Implementation Platform for their new Integrated Sign-Off Flow. The RTL-to-GDSII design flow deploys the advanced optimization technologies of Synopsys' Design Compiler® synthesis and IC Compiler physical implementation solutions, and the PrimeTime® sign-off and Star-RCXT™ extraction solutions - the industry yardsticks for IC design sign-off. The new flow is now available for 65-nanometer (nm) designs with planned extensions into other process technology nodes.

Synopsys, Inc. today announced that IC Compiler with Zroute technology drove silicon success for automotive microcontrollers of Infineon Technologies AG (FSE: IFX) (PinkSheets: IFNNY), a world leading automotive semiconductor provider.

IEEE 1801 Enabled Implementation Flow Qualified for 65- and 40-nm Designs

Synopsys, Inc. today announced that New Japan Radio Co., Ltd. (NJR), a leading supplier of linear integrated circuit devices for professional audio and high reliability automotive products, successfully deployed IC Compiler's multi-corner/multi-mode (MCMM) capability to achieve two times (2X) faster design closure. Previously, NJR performed half a dozen place-and-route iterations to close timing across all design modes and process corners, resulting in costly tapeout delays.

Synopsys, Inc. today announced that Toshiba Corporation deployed Synopsys' test solution to exceed the rigorous quality demands for its 65-nanometer (nm) multimedia chips. Toshiba engineers employed Synopsys' TetraMAX® automatic test pattern generation (ATPG) solution to achieve ultra-high test quality.

Synopsys, Inc., today announced that IC Compiler Zroute has been selected by EDN as the winner of this year's Innovation Award in the 'EDA: Design Creation and IP' category. Zroute is a new state-of-the-art full-chip router, built from the ground up to address forward-looking challenges in chip complexity and manufacturability.

Joint Collaboration Aims to Deliver Complete Design Flow for the 32-nm Process

Advanced Routing And Lower Clock Skew Seen As Critical For High-Performance Designs

Modern Architecture and Unified Design and Verification Environment Key to Productivity

Enhanced Composite Current Source (CCS) Modeling Technology Reduces Library Data Size by 75 Percent; Improves EDA Tool Efficiency by up to 60 Percent

Property and Parameter Definitions Contribution Will Help Enable Standardized PDKs and Custom IC Design Interoperability

Ease of Deployment Critical in Meeting Time-to-Market Requirements

Unique Power-Aware Test Capabilities Reduce Yield Loss

Faster Runtime, Enhanced Design Closure, and Increased Automation Boost Designer Productivity

Push-button flow and faster turnaround time speed up final stages of tapeout

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today unveiled its Galaxy Custom Designer solution, the industry's first modern-era mixed-signal implementation solution.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that MediaTek, Inc., a leading semiconductor company for wireless communications and digital media solutions, has adopted Synopsys' IC Compiler for its next-generation, high-performance 65-nanometer (nm) system-on-chip (SoC) designs.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that Oticon has taped out part of its next-generation digital signal processor (DSP) chipset for hearing-aid devices using Synopsys' IC Compiler design planning and place-and-route product, which is part of the Eclypse Low Power Solution.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today unveiled its new Design Compiler® Graphical synthesis product that shortens implementation time for system-on-chip (SoC) devices by helping RTL designers avoid wire-routing congestion problems that typically occur during detailed route.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the qualification and immediate availability of Synopsys' IC Compiler for designs targeting TSMC's latest 45-nanometer (nm) process.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced its multi-core initiative to deploy advanced parallel, threaded and other optimized compute technologies across its Discovery™ Verification and Galaxy™ Design platforms, and Design for Manufacturing (DFM) solutions.