| Aug 09, 2010 | Synopsys Galaxy Implementation Platform Used by TSMC for 28nm Process
Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities
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| Aug 05, 2010 | Synopsys Custom Design Tools Enable Creative Chips to Achieve First-pass Silicon Success
Unified Cell-Based and Custom Implementation Solution Key to Accelerating Time-to-Market
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| Jul 26, 2010 | Foveon Switches to Galaxy Custom Designer Solution to Accelerate Time-to-Tapeout
Synopsys Galaxy Custom Designer Enables First-pass Silicon Success on Foveon's Advanced Digital Sensor Product
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| Jun 10, 2010 | Samsung Achieves First-Pass 32nm Silicon Success Using Synopsys Galaxy Implementation Platform
Synopsys announced that Samsung Electronics' Foundry business (Samsung Foundry) has successfully taped out its first 32-nanometer (nm) system-on-chip (SoC) design using Synopsys' Galaxy™ Implementation Platform.
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| Sep 01, 2009 | Ubixum Achieves Product-Ready Design at First Silicon with Synopsys Galaxy Custom Designer Solution
Synopsys, Inc. today announced that Ubixum has used Synopsys' Galaxy Custom Designer™ implementation solution to successfully design its latest advanced image sensor chip.
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| Jul 24, 2009 | Synopsys Introduces Galaxy Constraint Analyzer to Improve Designer Productivity
Speeds RTL-to-GDSII Turnaround Time Through Look-ahead Constraint Analysis
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| Jul 20, 2009 | Synopsys Introduces IC Compiler In-Design Rail Analysis to Accelerate Design Closure
Synopsys, Inc. today introduced its In-Design Rail Analysis™ capability to accelerate design closure. Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.
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| Jun 09, 2009 | TSMC Selects Synopsys Galaxy Implementation Platform for Integrated Sign-off Flow
Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that TSMC selected Synopsys' Galaxy™ Implementation Platform for their new Integrated Sign-Off Flow. The RTL-to-GDSII design flow deploys the advanced optimization technologies of Synopsys' Design Compiler® synthesis and IC Compiler physical implementation solutions, and the PrimeTime® sign-off and Star-RCXT™ extraction solutions - the industry yardsticks for IC design sign-off. The new flow is now available for 65-nanometer (nm) designs with planned extensions into other process technology nodes.
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| Jun 09, 2009 | Synopsys IC Compiler with Zroute Technology Achieves Successful Tapeout for Infineon
Synopsys, Inc. today announced that IC Compiler with Zroute technology drove silicon success for automotive microcontrollers of Infineon Technologies AG (FSE: IFX) (PinkSheets: IFNNY), a world leading automotive semiconductor provider.
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| Jun 03, 2009 | Synopsys’ Eclypse Low Power Solution Enables Fujitsu Microelectronics to Cut Design Cycle by 30 Percent
IEEE 1801 Enabled Implementation Flow Qualified for 65- and 40-nm Designs
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| Jun 02, 2009 | Synopsys IC Compiler Multi-Corner/Multi-Mode Capability Delivers 2X Faster Design Closure
Synopsys, Inc. today announced that New Japan Radio Co., Ltd. (NJR), a leading supplier of linear integrated circuit devices for professional audio and high reliability automotive products, successfully deployed IC Compiler's multi-corner/multi-mode (MCMM) capability to achieve two times (2X) faster design closure. Previously, NJR performed half a dozen place-and-route iterations to close timing across all design modes and process corners, resulting in costly tapeout delays.
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| Apr 29, 2009 | Toshiba Exceeds Quality Goals for 65-nm Multimedia Chips Using Synopsys Test Solution
Synopsys, Inc. today announced that Toshiba Corporation deployed Synopsys' test solution to exceed the rigorous quality demands for its 65-nanometer (nm) multimedia chips. Toshiba engineers employed Synopsys' TetraMAX® automatic test pattern generation (ATPG) solution to achieve ultra-high test quality.
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| Apr 02, 2009 | Synopsys IC Compiler Zroute Wins EDN Innovation Award
Synopsys, Inc., today announced that IC Compiler Zroute has been selected by EDN as the winner of this year's Innovation Award in the 'EDA: Design Creation and IP' category. Zroute is a new state-of-the-art full-chip router, built from the ground up to address forward-looking challenges in chip complexity and manufacturability.
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| Dec 18, 2008 | Synopsys and STMicroelectronics Accelerate 32-Nanometer Readiness Delivering Optimized Standard Cell Library and Route-Rule Validation in IC Compiler
Joint Collaboration Aims to Deliver Complete Design Flow for the 32-nm Process
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| Dec 08, 2008 | STARC to Deploy Synopsys IC Compiler's Zroute and Clock Mesh Technologies in STARCAD-CEL
Advanced Routing And Lower Clock Skew Seen As Critical For High-Performance Designs
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| Nov 24, 2008 | Creative Chips Adopts Synopsys' Galaxy Custom Designer Mixed-Signal Implementation Solution
Modern Architecture and Unified Design and Verification Environment Key to Productivity
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| Nov 19, 2008 | Synopsys Unveils Breakthrough Modeling Technology to Address Library Data Size Explosion at 45-nm and Below
Enhanced Composite Current Source (CCS) Modeling Technology Reduces Library Data Size by 75 Percent; Improves EDA Tool Efficiency by up to 60 Percent
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| Nov 06, 2008 | Synopsys Makes Key Contribution to the IPL Alliance
Property and Parameter Definitions Contribution Will Help Enable Standardized PDKs and Custom IC Design Interoperability
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| Nov 03, 2008 | Ubixum Adopts Synopsys Galaxy Custom Designer Mixed-Signal Implementation Solution
Ease of Deployment Critical in Meeting Time-to-Market Requirements
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| Oct 28, 2008 | Synopsys DFT MAX Compression Achieves Mainstream Usage at 90 Nanometers and Below
Unique Power-Aware Test Capabilities Reduce Yield Loss
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| Sep 29, 2008 | Synopsys Delivers 2X Speed-Up With IC Compiler 2008.09
Faster Runtime, Enhanced Design Closure, and Increased Automation Boost Designer Productivity
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| Sep 24, 2008 | Synopsys Adds Incremental Signoff-Quality Design Rule Checking to IC Compiler
Push-button flow and faster turnaround time speed up final stages of tapeout
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| Sep 22, 2008 | Synopsys Enters Mixed-Signal Implementation Market With Galaxy Custom Designer
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today unveiled its Galaxy Custom Designer solution, the industry's first modern-era mixed-signal implementation solution.
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| Jun 03, 2008 | MediaTek Achieves Faster Time-to-Tapeout with IC Compiler
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that MediaTek, Inc., a leading semiconductor company for wireless communications and digital media solutions, has adopted Synopsys' IC Compiler for its next-generation, high-performance 65-nanometer (nm) system-on-chip (SoC) designs.
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