This white paper takes an in depth look at a variety of techniques to help you speed up your synthesis iterations. Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditionial and new techniques that accelerate design and debug iterations.
Synopsys

This paper examines the latest trends, tools and methodologies that you should consider before beginning your next FPGA project. Being aware of the issues and solutions will allow you to take full advantage of the vital resources and benefits offered by FPGAs and to navigate potential hurdles. Click here to register and download.
Synopsys

Timing-closure is a growing concern for FPGA designers, particularly with the recent introduction of multi-million gate architectures fabricated at the 90nm and 65nm technology nodes. It is not sufficient for a timing-closure solution- the entire flow, including synthesis - to only meet the required timing; such a solution must also minimize the number of time-consuming synthesis-place-route iterations and provide results that remain stable across multiple physical synthesis runs and during final routing.
Jeff Garrison, Director of Product Marketing, Synopsys’ Synplicity Business Group, May 2007

This paper first discusses where the various encryption and decryption steps occur in the design flow. Next, it introduces the conventional encryption techniques – specifically symmetric and asymmetric encryption algorithms – and explains the problems associated with these approaches in the context of an electronic design flow. Finally, a hybrid symmetric-asymmetric open solution is described that leverages existing technology, that fully addresses the needs of modern electronic design environments, and that would be easy to adopt by IP, EDA, and silicon vendors.
Andrew Dauman,Vice President, Engineering, Synopsys’ Synplicity Business Group, June 2006

This paper will consider the tools and techniques that may be used in the course of a verification cycle and willexamine the benefits and shortcomings of each.
The Synopsys Synplicity Business Group, May 2006

This paper first presents the main conventional synthesis approaches and explains the problems associated with these techniques. The paper then introduces the concepts underlying graph-based physical synthesis and shows how this technology uniquely addresses the requirements of today’s state-of-the-art FPGA architectures.
The Synopsys Synplicity Business Group, September 2005

In a typical FPGA design flow, most designers work from a written specification that contains architectural level drawings defining the major logic blocks, interfaces, and busses. The design manager begins to partition functionality based on the diagrams and to assign development based on the block’s functional descriptions. Each block is coded individually and may be simulated in a block-specific testbench. The team assembles the blocks into a device-level file where the ports are pins on the target device. The design is then ready to be compiled for simulation initiating the debug phase of development: simulation followed by hardware debug.
The Synopsys Synplicity Business Group, April 2005

This paper discusses in great detail the difficulties of implementing FPGA by contrasting FPGA with ASIC technologies. The benefits of physical synthesis are shown in the context of understanding the limits of conventional synthesis when applied to an FPGA design. There is also a discussion of pushbutton synthesis verses design planning.
The Synopsys Synplicity Business Group, September 2005