Discover how FPGA-based rapid prototyping is used as a natural progression to complement emulation when the shortening of development time is critical to the overall success of ASIC and SoC projects.
Neil Songcuan, Synopsys
Mar 31, 2010

Whether you are using FPGAs to verify your ASIC or as a final implementation platform, this webinar will illustrate techniques to help you speed up your synthesis iterations by a factor of 2 vs. traditional approaches, and achieve up to 2 times the turnaround time from RTL to board with better results stability from one run to the next. Techniques for more efficient debug and optional team design techniques are also covered.
Angela Sutton, Synopsys
Mar 03, 2010

Learn how to use the Synphony high-level synthesis tool to do architectural power exploration within days of a having a high level algorithm model in MATLAB or Simulink.
Chris Eddington, Director of Product Marketing, Synopsys; Josefina Hobbs, Technical Solutions Architect, Synopsys
Jan 19, 2010

This webinar discusses how the unique features of Altera's high-end Stratix-FPGAs combined with Synopsys high-performance rapid protoyping solutions enable new use modes and capabilities for algorithmic acceleration, as well as for highest performance rapid prototyping.
Synopsys
Oct 29, 2009

Off-the-shelf rapid prototyping boards lower cost, reduce risk and improve competitiveness
Juergen Jaeger, Director of Product Marketing, Confirma Rapid Prototyping, Synopsys
May 21, 2009

This 3-part series introduces Synopsys tools for FPGA users, including model-based algorithmic design, IP integration tools, tightly coupled constraint and analysis environments, integrated synthesis and placement, and on-board assertion-based verification linked to RTL simulation.
Doug Amos and Paul Schoukroun, Synopsys
Mar 09, 2009