As FPGAs grow more capable, they will increasingly replace ASIC devices for certain applications where bleeding-edge performance or extremely large volumes are not required. And as the prevalence of FPGAs as integral components of products continue to increase, debugging of these large devices will only grow more arduous. These trends will render already antiquated gate-level debugging techniques totally obsolete. Only with more advanced debugging tools will we be able to meet next-generation time-to-market demands. This article, by Jeff Garrison, Director of Product Marketing FPGA Synthesis tools, discusses the challenges of debugging large FPGA devices and provides insight into the tools and methodologies that alleviate some of these challenges.
Jan 19, 2010

Given the size and complexity of today’s FPGA designs, it is increasingly common for some form of design verification to be performed throughout the FPGA design process. While simulation and prototyping remain the standards for validating design functionality, verifying the FPGA netlist at various stages in the design flow has become increasingly important because of the logic manipulations that occur during FPGA synthesis.
Jul 22, 2008

With excellent tools available almost for free from FPGA companies, you might wonder why top notch design teams still pay for high-end FPGA tools from companies like Synplicity. This week, Synplicity helped us out with that question with new improvements to their top-of-the-line synthesis offering – Synplify Premier.
Jan 29, 2008

Timing-closure is a growing concern for FPGA designers, particularly with the recent introduction of multi-million gate architectures fabricated at the 90 nm and 65 nm technology nodes.
Jan 23, 2008