Synplify Pro
The Synplify Pro FPGA RTL logic synthesis software is the industry standard for producing high-performing, cost-effective FPGA designs. It’s unique Behavior Extracting Synthesis Technology® (B.E.S.T.™) performs optimization first at a high level before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, runs fast and supports very large design sizes. The Synplify Pro software supports the latest VHDL and Verilog language constructs including System Verilog and Verilog 2008. It supports implementation in all leading FPGA devices from a variety of FPGA vendors, including Actel, Altera, Lattice Semiconductor and Xilinx using a single easy-to-use interface, with the ability to perform incremental synthesis and fast incremental debugging.

Synplify Pro Datasheet

Synplify
The Synplify product is Synopsys entry-level FPGA synthesis tool.  It utilizes the Synplify Pro logic synthesis engine and is designed with a more simplified user interface for small design teams and ease of use.   See comparison chart  for viewing the features offered in the Synplify, Synplify Pro and Synplify Premier products.

HDL Analyst
Synopsys' HDL Analyst® tool provides designers with the ability to quickly debug and enhance their Verilog or VHDL code. This is accomplished by providing the designer with graphical representations of their design using a high-level (RTL) technology-independent and technology-specific schematic views. Cross-probing between these schematic views and HDL source code allows designers to immediately view the actual implementation of their design and analyze it for further improvement. HDL Analyst is optional for the Synplify product and included as a standard feature in Synplify Pro and Synplify Premier products.

HDL Analyst Datasheet