Synplify Premier
The Synplify Premier solution is the industry's most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes.

The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains optimization techniques that enhance DSP, IP and embedded design results. For ASIC prototypers, it delivers ASIC design file and DesignWare compatibility as well as tight integration with the Confirma Rapid Prototyping platform and FPGA vendor back-end tools as well as vendor embedded tools including Altera SoPC Builder and Xilinx EDK.

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The Synplify Premier product offers FPGA Designers and ASIC Prototypers, targeting single FPGA-based prototypes, with the most efficient method of design implementation and debug. The Synplify Premier software provides in-system verification of FPGAs, dramatically accelerates the debug process, and provides a rapid and incremental method for finding elusive design problems.
The Synplify Premier software advantages include:

• technology and vendor independence
• in-system debug
• fast timing closure
• RTL analysis
• DSP-friendly synthesis algorithms
• superior Quality of Results (QoR)

FAST Turnaround and Debug Flows

Synplify Premier offers users rapid feedback on their design projects and fast synthesis turnaround times. The product includes a fast synthesis mode which saves up to 50% on synthesis runtime for a small reduction in QoR, giving designers the ability to quickly implement design netlists or the design on the board to gain the rapid feedback necessary to tune the RTL and constraints. Synplify Premier provides accurate timing and utilization data immediately after physical synthesis without the need to run place and route tools. And, Synplify Premier’s physical synthesis timing and utilization reports are based on actual placement and thus tightly correlate with actual place and route results.

• fast turnaround time mode for logic synthesis saves up to 50% on runtime
• accurate timing and utilization data
• placement tightly correlates with results of Place & Route tools

Reach Timing Goals Quickly with Graph-based Physical Synthesis
Today’s high-density FPGAs make it increasingly difficult for designers to meet their aggressive timing goals quickly. Synopsys' Synplify Premier product addresses the timing closure challenge with its patented Graph-based physical synthesis technology.
Graph-based Physical Synthesis offers:

• patented technology
• improved timing closure through estimations that are tightly correlated with final post place & route timing
  • 90% of designs are within 10% of actual timing
• assurance that correct critical paths are being optimized
• significant reduction in design iterations and development time

Graph-based physical synthesis provides tight correlation to final timing

Find Bugs Quickly
The Synplify Premier software provides a rapid method of finding functional errors in FPGA designs by providing simulator-like visibility into live-running hardware. The methodology is based on technology found in the Identify® RTL Debugger - the first and only tool that allows designers to instrument and debug directly in RTL source code.
Synplify Premier’s debugger technology provides designers with:

• ability to add probes and trigger conditions in familiar RTL source code
• ability to see sequence of captured results annotated in context to the RTL code
• fast, incremental debug flow ability to bypass time-consuming iterations through place & route

DSP Friendly Synthesis
As DSP functionality within FPGAs continues to rise, the Synplify Premier software’s DSP-aware mapping technology takes full advantage of the dedicated DSP structures and memories built in to today’s modern FPGAs.
The Synplify Premier tool’s DSP aware synthesis provides:

• DSP-friendly synthesis algorithms
• RTL DSP functions automatically mapped into vendors’ DSP hardware
• tight integration with Synopsys' Synplify DSP software

ASIC Verification using Single FPGA-based Prototypes
As a part of Synopsys' Confirma ASIC/ASSP Verification Platform, the Synplify Premier solution offers the most comprehensive system for implementing single FPGA-based ASIC prototypes.
Synplify Premier’s ASIC prototyping features offer:

• built-in gated clock conversion
• Synopsys DesignWare® Support
• tight integration with Synopsys' HAPS™ High-performance ASIC Prototyping System

HAPS-A31 prototyping board	HAPS-51 Prototyping board

System-Level Implementation and IP Integration
The System Designer™ capability, a key component of the ReadyIP program, allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then easily implement it into a variety of FPGA vendor devices.
The System Designer capability offers:

• the use of Spirit IP-XACT Compliant IP
• the ability to Configure And Interconnect IP For System
• easy Drag & Drop Connectivity
• easy Reuse Of In-house, Proprietary IP
• Eclipse-based format

Access To Third Party IP for Evaluation and Download
The ReadyIP Initiative is a program that simplifies the access, evaluation, and use of IP for FPGA-based system design. It is an encrypted design methodology for FPGA implementation that allows users to incorporate and easily integrate IP from several third-party vendors within their designs using Synopsys’ industry-standard synthesis environments, the Synplify Pro® and/or Synplify® Premier solutions.
The ReadyIP initiative offers:

• standards-based, accessible and secure IP distribution environment
• easy-to-Use IP evaluation mechanism
• IP configuration and assembly integrated into Synopsys' synthesis products
• partnership with leading IP vendors