Normally, a design team will tackle a new project on a new, smaller-geometry process and realize the benefits of increased performance and lower cost per chip. This white paper addresses the reverse of this situation, in which a functioning 65nm analog and mixed-signal design is “blown up” to a 130nm process to help mitigate the higher mask costs of the smaller geometry.
Bob Lefferts, R&D Group Director, Analog and Mixed-signal IP, Synopsys; Neel Gopalan, AMS CAE, Synopsys

SmartDRD is a new, innovative technology built into Galaxy Custom Designer™ Layout Editor (LE) for interactive DRC violation visualization, detection and correction, commonly known as design-rule-driven (DRD) editing
Synopsys

Advances in modern-era user interface and software design techniques have taken root in custom design EDA tools, leading to a new potential for huge productivity savings and faster time-to-results. This white paper explores these techniques as applied to the creative processes of custom and analog design, including industry-recognized use models, advanced techniques in user interface, open language programmable cells and extraction for post-layout simulation.
Les Spruiell and Chris Shaw Custom Design Product Marketing, Synopsys, Inc.

Consider the number of checks that an IC design team has to go through before tape-out. In each company, chip failures ultimately translate into additional checks in the sign-off flow. Technology and design trends are responsible for further increasing the number of checks.
Bradley Geden Product Marketing Manager, AMS Circuit Simulation, Synopsys, Inc.

Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2-4x with every new process generation as chip transistor counts double and new parasitic effects come into play. The Synopsys StarRC™ extraction solution offers a wide range of features to boost the simulation performance and capacity of transistor-level custom digital, analog/mixed-signal and memory designs.
Omar Shah, Corporate Application Engineer; Shekhar Kapoor, Marketing Manager

Resolving correlation issues is a time consuming step and is all the more challenging when it has to be done across multiple corners and modes. Tight correlation to signoff is critical for faster time to results.
Ashwini Mulgaonkar, Synopsys Implementation Group

Currently, most EDA tools do not provide a solution that addresses the limitations of a custom datapath flow. This paper discusses datapath designs, benefits, limitations, and the use of an automated datapath design capability that allows both custom and ASIC designers to meet aggressive design objectives with ever-tighter project deadlines.
Jafar Safdar, Synopsys Implementation Group

There are numerous techniques to achieve a low-power design and several approaches to structuring the flow. As a starting point, high performance designs require a benchmark proven low-skew, low-insertion delay CTS solution. Correlation to industry standard sign-off engines for accuracy and minimum data format translations are required to achieve fast design closure. The optimal solution includes complete low power capability throughout the design flow. This paper addresses low power design issues and includes technologies and techniques to achieve high performance, low power design goals.
Harvey Toyama, Synopsys Implementation Group

There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process. This paper provides a production-proven example of this flow.
Elango Velayutham